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Hi Alex,

The machine of X870E and navi10 is quite unique, and I need to find a machine 
to verify this issue.
But this patch is necessary as it is a coding issue confirmed with Kenneth.

Best Regards,
Kevin

-----Original Message-----
From: amd-gfx <[email protected]> On Behalf Of Alex Deucher
Sent: Thursday, December 11, 2025 23:27
To: Wang, Yang(Kevin) <[email protected]>
Cc: [email protected]; Zhang, Hawking <[email protected]>; 
Deucher, Alexander <[email protected]>; Feng, Kenneth 
<[email protected]>
Subject: Re: [PATCH] drm/amd/pm: fix wrong pcie parameter on navi10

On Thu, Dec 11, 2025 at 9:01 AM Alex Deucher <[email protected]> wrote:
>
> On Thu, Dec 11, 2025 at 12:24 AM Yang Wang <[email protected]> wrote:
> >
> > fix wrong pcie dpm parameter on navi10
> >
> > Fixes: 1a18607c07bb ("drm/amd/pm: override pcie dpm parameters only if it 
> > is necessary")
>
> Assuming this fixes the gitlab ticket:
>
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4671

per the reporter, this does not fix the issue.

Alex

>
> Acked-by: Alex Deucher <[email protected]>
>
> >
> > Signed-off-by: Yang Wang <[email protected]>
> > Co-developed-by: Kenneth Feng <[email protected]>
> > ---
> >  drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > index 882830770b79..0c26fe6fb949 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > @@ -2216,8 +2216,8 @@ static int navi10_update_pcie_parameters(struct 
> > smu_context *smu,
> >                                                                         
> > pptable->PcieLaneCount[i] > pcie_width_cap ?
> >                                                                         
> > pcie_width_cap : pptable->PcieLaneCount[i];
> >                         smu_pcie_arg = i << 16;
> > -                       smu_pcie_arg |= pcie_gen_cap << 8;
> > -                       smu_pcie_arg |= pcie_width_cap;
> > +                       smu_pcie_arg |= 
> > dpm_context->dpm_tables.pcie_table.pcie_gen[i] << 8;
> > +                       smu_pcie_arg |= 
> > dpm_context->dpm_tables.pcie_table.pcie_lane[i];
> >                         ret = smu_cmn_send_smc_msg_with_param(smu,
> >                                                         
> > SMU_MSG_OverridePcieParameters,
> >                                                         smu_pcie_arg,
> > --
> > 2.34.1
> >

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