From: Mukul Joshi <[email protected]> Add a generic function to map IH node-id to XCC instance.
Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 33 ++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 453520d374a08..d9af479bafb78 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -692,6 +692,18 @@ static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); } +static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) +{ + int xcc = (ih_node & 0x7) - 2 + (ih_node >> 3) * 4; + + if (xcc < 0 || xcc >= hweight8(adev->gfx.xcc_mask)) { + dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); + return -EINVAL; + } + + return xcc; +} + static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = { .get_gpu_clock_counter = &gfx_v12_1_get_gpu_clock_counter, .select_se_sh = &gfx_v12_1_xcc_select_se_sh, @@ -700,6 +712,7 @@ static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = { .read_wave_vgprs = &gfx_v12_1_read_wave_vgprs, .select_me_pipe_q = &gfx_v12_1_select_me_pipe_q, .update_perfmon_mgcg = &gfx_v12_1_update_perf_clk, + .ih_node_to_logical_xcc = &gfx_v12_1_ih_to_xcc_inst, }; static int gfx_v12_1_gpu_early_init(struct amdgpu_device *adev) @@ -3407,7 +3420,7 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - int i; + int i, xcc_id; u8 me_id, pipe_id, queue_id; struct amdgpu_ring *ring; uint32_t mes_queue_id = entry->src_data[0]; @@ -3430,6 +3443,10 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; queue_id = (entry->ring_id & 0x70) >> 4; + xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); + + if (xcc_id == -EINVAL) + return -EINVAL; switch (me_id) { case 0: @@ -3441,7 +3458,9 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, case 1: case 2: for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; + ring = &adev->gfx.compute_ring + [i + + xcc_id * adev->gfx.num_compute_rings]; /* Per-queue interrupt is supported for MEC starting from VI. * The interrupt can only be enabled/disabled per pipe instead * of per queue. @@ -3509,11 +3528,15 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, { u8 me_id, pipe_id, queue_id; struct amdgpu_ring *ring; - int i; + int i, xcc_id; me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; queue_id = (entry->ring_id & 0x70) >> 4; + xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); + + if (xcc_id == -EINVAL) + return; switch (me_id) { case 0: @@ -3527,7 +3550,9 @@ static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, case 1: case 2: for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; + ring = &adev->gfx.compute_ring + [i + + xcc_id * adev->gfx.num_compute_rings]; if (ring->me == me_id && ring->pipe == pipe_id && ring->queue == queue_id) drm_sched_fault(&ring->sched); -- 2.51.1
