On 12/5/25 22:49, Philip Yang wrote: > For gfx version >= 9.4.3, bind MQD in GART with mtype RW to enable > caching, to reduce queue switch latency. > > Remove the redundant mtype definition in amdgpu_vm.h. > > Call amdgpu_gmc_get_vm_pte with AMDGPU_VM_MTYPE_ to get ASIC specific > mtype. > > Signed-off-by: Philip Yang <[email protected]>
Looks reasonable to me, but I can't fully check the technical correctness without digging through tons of documents. Acked-by: Christian König <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 ++++++- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 --- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > index 0f83d140b6ae..4f8bc7f35cdc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > @@ -853,7 +853,12 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct > amdgpu_device *adev, > int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); > uint64_t page_idx, pages_per_xcc; > int i; > - uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC); > + uint64_t ctrl_flags = flags; > + > + amdgpu_gmc_get_vm_pte(adev, NULL, NULL, AMDGPU_VM_MTYPE_NC, > &ctrl_flags); > + > + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 3)) > + amdgpu_gmc_get_vm_pte(adev, NULL, NULL, AMDGPU_VM_MTYPE_RW, > &flags); > > pages_per_xcc = total_pages; > do_div(pages_per_xcc, num_xcc); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > index 139642eacdd0..e34c8f854b2f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > @@ -100,9 +100,6 @@ struct amdgpu_bo_vm; > (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \ > AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) > > -#define AMDGPU_MTYPE_NC 0 > -#define AMDGPU_MTYPE_CC 2 > - > #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ > | AMDGPU_PTE_SNOOPED \ > | AMDGPU_PTE_EXECUTABLE \
