From: Mukul Joshi <[email protected]> Revert the change to enable retry based thrashing prevention on GFX 12.1.0 for now as its causing data mismatch and slowness issues with multiple HIP tests.
Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index edd5b41a1e395..da01903113f40 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2512,17 +2512,6 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) { uint32_t val; - /* Setup the TCP Thrashing control register */ - val = RREG32_SOC15(GC, 0, regTCP_UTCL0_THRASHING_CTRL); - - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, THRASHING_EN, 0x2); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_DOWN_EN, 0x0); - val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, - RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x0); - - WREG32_SOC15(GC, 0, regTCP_UTCL0_THRASHING_CTRL, val); - /* Set the TCP UTCL0 register to enable atomics */ val = RREG32_SOC15(GC, 0, regTCP_UTCL0_CNTL1); val = REG_SET_FIELD(val, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); -- 2.51.1
