On 11/7/25 16:57, Timur Kristóf wrote: > VCE1 is the Video Coding Engine 1.0 found in SI GPUs. > Add support for the VCE1 IP block, which is the last > missing piece for fully-featured SI support in amdgpu. > Co-developed by Alexandre Demers. > > This VCE1 implementation is based on: > VCE2 code in amdgpu > VCE1 code in radeon > Research by Alexandre > Suggestions from Christian > > The biggest challenge was getting the firmware > validation mechanism to work correctly. Due to > some limitations in the HW, the VCE1 requires > the VCPU BO to be located at a low 32-bit address. > This was achieved by placing the GART in the > LOW address space and manually mapping the > VCPU BO in the GART page table. > > Also hook up the VCE1 to the DPM. > > Tested on the following HW: > Radeon R9 280X (Tahiti) > Radeon HD 7990 (Tahiti) > FirePro W9000 (Tahiti) > Radeon R7 450 (Cape Verde) > > Changes in v2: > - Refactor the new GART helper to be reusable > - Reduce reserved GART size from 16 MiB to 2 MiB > - Clear VCPU BO only on device creation > - Save VCPU BO on suspend, restore on resume > - Rework how an empty codec list is handled > - Add different workaround for FirePro W9000 > - Address all other feedback from the review > > Changes in v3: > - Drop patch to return empty codec list when VCE is not present, > this is actually not needed. > - Instead of relying on gmc_v6 to set the GART space before GTT, > add a new function amdgpu_vce_required_gart_pages() which is > called from amdgpu_gtt_mgr_init() directly. > > Changes in v4: > - Clear VCPU BO on resume like in v1 > - Don't unmap/unreserve BO on resume > > Looking forward to reviews and feedback!
I've just pushed the whole set to amd-staging-drm-next. There is a slight possibility that the CI system find something (because of patch #4), but I strongly doubt it. Thanks a lot for taking care of this, Christian. > > Timur Kristóf (12): > drm/amdgpu/gmc6: Place gart at low address range > drm/amdgpu/gart: Add helper to bind VRAM pages (v2) > drm/amdgpu/ttm: Use GART helper to map VRAM pages (v2) > drm/amdgpu/vce: Move firmware load to amdgpu_vce_early_init > drm/amdgpu/vce: Clear VCPU BO, don't unmap/unreserve (v4) > drm/amdgpu/vce1: Clean up register definitions > drm/amdgpu/vce1: Load VCE1 firmware > drm/amdgpu/vce1: Implement VCE1 IP block (v2) > drm/amdgpu/vce1: Ensure VCPU BO is in lower 32-bit address space (v3) > drm/amd/pm/si: Hook up VCE1 to SI DPM > drm/amdgpu/vce1: Enable VCE1 on Tahiti, Pitcairn, Cape Verde GPUs > drm/amdgpu/vce1: Workaround PLL timeout on FirePro W9000 > > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 36 + > drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 3 + > drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 174 ++-- > drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 3 + > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/si.c | 22 +- > drivers/gpu/drm/amd/amdgpu/sid.h | 40 - > drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 839 ++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/vce_v1_0.h | 32 + > drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 5 + > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 + > drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 5 + > .../drm/amd/include/asic_reg/vce/vce_1_0_d.h | 5 + > .../include/asic_reg/vce/vce_1_0_sh_mask.h | 10 + > drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 18 +- > 18 files changed, 1080 insertions(+), 134 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v1_0.h >
