From: Dave Airlie <airl...@redhat.com>
This just aligns a few things with kernel style.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 ++--
drivers/gpu/drm/amd/display/dc/dc_types.h | 16 ++++----
.../display/dc/dce110/dce110_timing_generator.c | 4 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 ++++----
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 46 +++++++++++-----------
.../amd/display/include/grph_object_ctrl_defs.h | 20 +++++-----
6 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 888d268..3c323c1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1473,10 +1473,10 @@ void decide_link_settings(struct dc_stream_state
*stream,
return;
}
- /* search for the minimum link setting that:
- * 1. is supported according to the link training result
- * 2. could support the b/w requested by the timing
- */
+ /* search for the minimum link setting that:
+ * 1. is supported according to the link training result
+ * 2. could support the b/w requested by the timing
+ */
while (current_link_setting.link_rate <=
link->verified_link_cap.link_rate) {
link_bw = bandwidth_in_kbps_from_link_settings(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index a47f7472..6b891fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -429,14 +429,14 @@ union audio_sample_rates {
};
struct audio_speaker_flags {
- uint32_t FL_FR:1;
- uint32_t LFE:1;
- uint32_t FC:1;
- uint32_t RL_RR:1;
- uint32_t RC:1;
- uint32_t FLC_FRC:1;
- uint32_t RLC_RRC:1;
- uint32_t SUPPORT_AI:1;
+ uint32_t FL_FR:1;
+ uint32_t LFE:1;
+ uint32_t FC:1;
+ uint32_t RL_RR:1;
+ uint32_t RC:1;
+ uint32_t FLC_FRC:1;
+ uint32_t RLC_RRC:1;
+ uint32_t SUPPORT_AI:1;
};
struct audio_speaker_info {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index bcd544d..67ac737 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1238,8 +1238,8 @@ void dce110_timing_generator_setup_global_swap_lock(
DCP_GSL_CONTROL,
DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
- /* Keep signal low (pending high) during 6 lines.
- * Also defines minimum interval before re-checking signal. */
+ /* Keep signal low (pending high) during 6 lines.
+ * Also defines minimum interval before re-checking signal. */
set_reg_field_value(value,
HFLIP_CHECK_DELAY,
DCP_GSL_CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c4875c3..d3fee15 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2396,14 +2396,14 @@ static void program_all_pipe_in_tree(
dcn10_power_on_fe(dc, pipe_ctx, context);
/* temporary dcn1 wa:
- * watermark update requires toggle after a/b/c/d sets are
programmed
- * if hubp is pg then wm value doesn't get properaged to hubp
- * need to toggle after ungate to ensure wm gets to hubp.
- *
- * final solution: we need to get SMU to do the toggle as
- * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we
should have
- * both driver and fw accessing same register
- */
+ * watermark update requires toggle after a/b/c/d sets are
programmed
+ * if hubp is pg then wm value doesn't get properaged to hubp
+ * need to toggle after ungate to ensure wm gets to hubp.
+ *
+ * final solution: we need to get SMU to do the toggle as
+ * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we
should have
+ * both driver and fw accessing same register
+ */
toggle_watermark_change_req(dc->hwseq);
update_dchubp_dpp(dc, pipe_ctx, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index c808848..a28495d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -697,37 +697,37 @@ static void min10_set_vm_context0_settings(struct
mem_input *mem_input,
}
static void min_set_viewport(
- struct mem_input *mem_input,
- const struct rect *viewport,
- const struct rect *viewport_c)
+ struct mem_input *mem_input,
+ const struct rect *viewport,
+ const struct rect *viewport_c)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
- REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
- PRI_VIEWPORT_WIDTH, viewport->width,
- PRI_VIEWPORT_HEIGHT, viewport->height);
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
+ PRI_VIEWPORT_WIDTH, viewport->width,
+ PRI_VIEWPORT_HEIGHT, viewport->height);
- REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
- PRI_VIEWPORT_X_START, viewport->x,
- PRI_VIEWPORT_Y_START, viewport->y);
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
+ PRI_VIEWPORT_X_START, viewport->x,
+ PRI_VIEWPORT_Y_START, viewport->y);
- /*for stereo*/
- REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
- SEC_VIEWPORT_WIDTH, viewport->width,
- SEC_VIEWPORT_HEIGHT, viewport->height);
+ /*for stereo*/
+ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
+ SEC_VIEWPORT_WIDTH, viewport->width,
+ SEC_VIEWPORT_HEIGHT, viewport->height);
- REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
- SEC_VIEWPORT_X_START, viewport->x,
- SEC_VIEWPORT_Y_START, viewport->y);
+ REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
+ SEC_VIEWPORT_X_START, viewport->x,
+ SEC_VIEWPORT_Y_START, viewport->y);
- /* DC supports NV12 only at the moment */
- REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
- PRI_VIEWPORT_WIDTH_C, viewport_c->width,
- PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
+ /* DC supports NV12 only at the moment */
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
+ PRI_VIEWPORT_WIDTH_C, viewport_c->width,
+ PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
- REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
- PRI_VIEWPORT_X_START_C, viewport_c->x,
- PRI_VIEWPORT_Y_START_C, viewport_c->y);
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
+ PRI_VIEWPORT_X_START_C, viewport_c->x,
+ PRI_VIEWPORT_Y_START_C, viewport_c->y);
}
void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index 92fe00f..7a9b43f 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -183,9 +183,9 @@ struct dc_firmware_info {
};
struct step_and_delay_info {
- uint32_t step;
- uint32_t delay;
- uint32_t recommended_ref_div;
+ uint32_t step;
+ uint32_t delay;
+ uint32_t recommended_ref_div;
};
struct spread_spectrum_info {
@@ -266,16 +266,16 @@ struct transmitter_configuration {
#define NUMBER_OF_AVAILABLE_SCLK 5
struct i2c_reg_info {
- unsigned char i2c_reg_index;
- unsigned char i2c_reg_val;
+ unsigned char i2c_reg_index;
+ unsigned char i2c_reg_val;
};
struct ext_hdmi_settings {
- unsigned char slv_addr;
- unsigned char reg_num;
- struct i2c_reg_info reg_settings[9];
- unsigned char reg_num_6g;
- struct i2c_reg_info reg_settings_6g[3];
+ unsigned char slv_addr;
+ unsigned char reg_num;
+ struct i2c_reg_info reg_settings[9];
+ unsigned char reg_num_6g;
+ struct i2c_reg_info reg_settings_6g[3];
};
--
2.9.5
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