This commit introduces a diagram and a set of information that details the different sets of schedulers available in the SE.
Cc: Alex Deucher <alexander.deuc...@amd.com> Cc: Christian König <christian.koe...@amd.com> Cc: Timur Kristóf <timur.kris...@gmail.com> Signed-off-by: Rodrigo Siqueira <sique...@igalia.com> --- Documentation/gpu/amdgpu/gc/cu.svg | 437 ++++++++++++++++++++++++++ Documentation/gpu/amdgpu/gc/index.rst | 32 +- 2 files changed, 463 insertions(+), 6 deletions(-) create mode 100644 Documentation/gpu/amdgpu/gc/cu.svg diff --git a/Documentation/gpu/amdgpu/gc/cu.svg b/Documentation/gpu/amdgpu/gc/cu.svg new file mode 100644 index 000000000000..10bdb3e24b65 --- /dev/null +++ b/Documentation/gpu/amdgpu/gc/cu.svg @@ -0,0 +1,437 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!-- Created with Inkscape (http://www.inkscape.org/) --> + +<svg + width="411.03354mm" + height="213.48447mm" + viewBox="0 0 411.03354 213.48447" + version="1.1" + id="svg1" + inkscape:version="1.4 (e7c3feb100, 2024-10-09)" + sodipodi:docname="cu.svg" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"; + 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+GPU/APU, and each SE has multiple Compute Units (CU). From the diagram, you can +see that CUs have a block named Schedulers. The reason the name is in plural is +because this hardware block is a combination of different micro-schedules: CP, +CPF, CPC, and CPG. + The component that acts as the front end between the CPU and the GPU is called -the Command Processor (CP). This component is responsible for providing greater +CP (Command Processor). This component is responsible for providing greater flexibility to the GC since CP makes it possible to program various aspects of the GPU pipeline. CP also coordinates the communication between the CPU and GPU via a mechanism named **Ring Buffers**, where the CPU appends information to -the buffer while the GPU removes operations. It is relevant to highlight that a -CPU can add a pointer to the Ring Buffer that points to another region of -memory outside the Ring Buffer, and CP can handle it; this mechanism is called -**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and -writes the operations to the correct hardware blocks. +the buffer while the GPU removes operations. Finally, CP is also responsible +for handling Indirect Buffers (IB). + +After CP completes the first set of processing, which includes separate command +packets specific to GFX and Compute, other blocks step in. To handle commands +for the compute block, CPC (Command Processor Command) takes over, and for +handling Graphics operations, the CPG (Command Processor Graphics) takes +action. Another essential block to ensure the optimal utilization of CPC and +CPG is the CPF (Command Processor Fetcher), which helps these blocks to be +constantly fed. Note that CPG contains the PFP (Pre-Fetch Parser), ME +(MicroEngine), and CE (Constant Engine) in the case of chips that support it. +CPC contains MEC (MicroEngine Compute), and CPF is another hardware block that +provides services to CPG and CPC. + Graphics (GFX) and Compute Microcontrollers ------------------------------------------- -- 2.47.2
