>From MES version 0x81, it provide the new API INV_TLBS that support
invalidate tlbs with PASID.
Signed-off-by: Shaoyun Liu <shaoyun....@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 27 ++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 20 ++++++++++++
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 43 +++++++++++++++++++++++++
3 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index c0d2c195fe2e..46235b8726f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -280,6 +280,30 @@ struct mes_reset_queue_input {
bool is_kq;
};
+enum amdgpu_mes_hub_id {
+ AMDGPU_MES_GC_HUB0 = 0,
+ AMDGPU_MES_GC_HUB1 = 1,
+ AMDGPU_MES_GC_HUB2 = 2,
+ AMDGPU_MES_GC_HUB3 = 3,
+ AMDGPU_MES_GC_HUB4 = 4,
+ AMDGPU_MES_GC_HUB5 = 5,
+ AMDGPU_MES_GC_HUB6 = 6,
+ AMDGPU_MES_GC_HUB7 = 7,
+ AMDGPU_MES_MM_HUB00 = 8,
+ AMDGPU_MES_MM_HUB01 = 9,
+ AMDGPU_MES_MM_HUB02= 10,
+ AMDGPU_MES_MM_HUB03 = 11,
+ AMDGPU_MES_MM_HUB10 = 12,
+ AMDGPU_MES_MM_HUB11 = 13,
+};
+
+struct mes_inv_tlbs_pasid_input {
+ uint32_t xcc_id;
+ uint16_t pasid;
+ uint8_t hub_id;
+ uint8_t flush_type;
+};
+
enum mes_misc_opcode {
MES_MISC_OP_WRITE_REG,
MES_MISC_OP_READ_REG,
@@ -367,6 +391,9 @@ struct amdgpu_mes_funcs {
int (*reset_hw_queue)(struct amdgpu_mes *mes,
struct mes_reset_queue_input *input);
+
+ int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes,
+ struct mes_inv_tlbs_pasid_input *input);
};
#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index feb92e107af8..b5be6c7838aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -339,6 +339,26 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct
amdgpu_device *adev,
uint16_t queried;
int vmid, i;
+ if (adev->enable_uni_mes &&
adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready &&
+ (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x81) {
+ struct mes_inv_tlbs_pasid_input input = {0};
+ input.pasid = pasid;
+ input.flush_type = flush_type;
+ input.hub_id = AMDGPU_GFXHUB(0);
+ /* MES will invalidate all gc_hub for the device from master */
+ adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input);
+ if (all_hub) {
+ /* Only need to invalidate mm_hub now */
+ for_each_set_bit(i, adev->vmhubs_mask,
AMDGPU_MAX_VMHUBS) {
+ if (i < AMDGPU_MMHUB0_START)
+ continue;
+ input.hub_id = i;
+
adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input);
+ }
+ }
+ return;
+ }
+
for (vmid = 1; vmid < 16; vmid++) {
bool valid;
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 6b222630f3fa..6740383f7721 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -108,6 +108,7 @@ static const char *mes_v12_0_opcodes[] = {
"SET_SE_MODE",
"SET_GANG_SUBMIT",
"SET_HW_RSRC_1",
+ "INVALIDATE_TLBS",
};
static const char *mes_v12_0_misc_opcodes[] = {
@@ -879,6 +880,47 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
offsetof(union MESAPI__RESET, api_status));
}
+static int mes_v12_inv_tlb_convert_hub_id(enum amdgpu_mes_hub_id id)
+{
+ int mes_hub_id = id;
+ /*
+ * MES doesn't support invalidate gc_hub on slave xcc individually
+ * master xcc will invalidate all gc_hub for the partition
+ */
+ if (id == 0)
+ return 0;
+ if (id < AMDGPU_MMHUB0_START)
+ return -EINVAL;
+
+ mes_hub_id -= AMDGPU_MMHUB0_START - 1;
+ /* gfx12 only support maximum one mmhub */
+ return (mes_hub_id > 1) ? -EINVAL: mes_hub_id;
+}
+static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes,
+ struct mes_inv_tlbs_pasid_input *input)
+{
+ union MESAPI__INV_TLBS mes_inv_tlbs;
+
+ memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs));
+
+ mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER;
+ mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS;
+ mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+ mes_inv_tlbs.invalidate_tlbs.inv_sel = 0;
+ mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type;
+ mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid;
+
+ /*convert amdgpu_mes_hub_id to mes expected hub_id */
+ mes_inv_tlbs.invalidate_tlbs.hub_id =
mes_v12_inv_tlb_convert_hub_id(input->hub_id);
+ if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0)
+ return -EINVAL;
+ return mes_v12_0_submit_pkt_and_poll_completion(mes,
AMDGPU_MES_KIQ_PIPE,
+ &mes_inv_tlbs, sizeof(mes_inv_tlbs),
+ offsetof(union MESAPI__INV_TLBS, api_status));
+
+}
+
static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
.add_hw_queue = mes_v12_0_add_hw_queue,
.remove_hw_queue = mes_v12_0_remove_hw_queue,
@@ -888,6 +930,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
.resume_gang = mes_v12_0_resume_gang,
.misc_op = mes_v12_0_misc_op,
.reset_hw_queue = mes_v12_0_reset_hw_queue,
+ .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid,
};
static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
--
2.34.1
