[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Reviewed-by: Leo Liu <leo....@amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of David
> Rosca
> Sent: August 18, 2025 5:43 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Rosca, David <david.ro...@amd.com>
> Subject: [PATCH 2/2] drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1
> at any time
>
> There is no reason to require this to happen on first submitted IB only.
> We need to wait for the queue to be idle, but it can be done at any time
> (including when there are multiple video sessions active).
>
> Signed-off-by: David Rosca <david.ro...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++++++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 12 ++++++++----
> 2 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 95173156f956..f3085137ba08 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -1886,15 +1886,19 @@ static int vcn_v3_0_limit_sched(struct
> amdgpu_cs_parser *p,
> struct amdgpu_job *job)
> {
> struct drm_gpu_scheduler **scheds;
> -
> - /* The create msg must be in the first IB submitted */
> - if (atomic_read(&job->base.entity->fence_seq))
> - return -EINVAL;
> + struct dma_fence *fence;
>
> /* if VCN0 is harvested, we can't support AV1 */
> if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
> return -EINVAL;
>
> + /* wait for all jobs to finish before switching to instance 0 */
> + fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
> + if (fence) {
> + dma_fence_wait(fence, false);
> + dma_fence_put(fence);
> + }
> +
> scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
> [AMDGPU_RING_PRIO_DEFAULT].sched;
> drm_sched_entity_modify_sched(job->base.entity, scheds, 1); diff --
> git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 23b98f011879..235fc9e01dd7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -1805,15 +1805,19 @@ static int vcn_v4_0_limit_sched(struct
> amdgpu_cs_parser *p,
> struct amdgpu_job *job)
> {
> struct drm_gpu_scheduler **scheds;
> -
> - /* The create msg must be in the first IB submitted */
> - if (atomic_read(&job->base.entity->fence_seq))
> - return -EINVAL;
> + struct dma_fence *fence;
>
> /* if VCN0 is harvested, we can't support AV1 */
> if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
> return -EINVAL;
>
> + /* wait for all jobs to finish before switching to instance 0 */
> + fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
> + if (fence) {
> + dma_fence_wait(fence, false);
> + dma_fence_put(fence);
> + }
> +
> scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
> [AMDGPU_RING_PRIO_0].sched;
> drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
> --
> 2.43.0
