There no need to save the ring ptrs. Just reset them.
This cleans up a conditional in the resume code.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 27 +++++++++-----------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 103e5ec7aa63b..455f1a8a07ad4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -474,12 +474,11 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev,
bool enable)
*
* @adev: amdgpu_device pointer
* @i: instance
- * @restore: used to restore wptr when restart
*
- * Set up the gfx DMA ring buffers and enable them. On restart, we will
restore wptr and rptr.
+ * Set up the gfx DMA ring buffers and enable them.
* Return 0 for success.
*/
-static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i,
bool restore)
+static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i)
{
struct amdgpu_ring *ring;
u32 rb_cntl, ib_cntl;
@@ -506,17 +505,10 @@ static int sdma_v6_0_gfx_resume_instance(struct
amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
/* Initialize the ring buffer's read and write pointers */
- if (restore) {
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
- } else {
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_RPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_RPTR_HI), 0);
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_WPTR), 0);
- WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_WPTR_HI), 0);
- }
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_RPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_RPTR_HI), 0);
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_WPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_WPTR_HI), 0);
/* setup the wptr shadow polling */
wptr_gpu_addr = ring->wptr_gpu_addr;
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
@@ -537,8 +529,7 @@ static int sdma_v6_0_gfx_resume_instance(struct
amdgpu_device *adev, int i, bool
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
- if (!restore)
- ring->wptr = 0;
+ ring->wptr = 0;
/* before programing wptr to a less value, need set minor_ptr_update
first */
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
@@ -633,7 +624,7 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
int i, r;
for (i = 0; i < adev->sdma.num_instances; i++) {
- r = sdma_v6_0_gfx_resume_instance(adev, i, false);
+ r = sdma_v6_0_gfx_resume_instance(adev, i);
if (r)
return r;
}
@@ -1592,7 +1583,7 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring,
if (r)
return r;
- r = sdma_v6_0_gfx_resume_instance(adev, i, true);
+ r = sdma_v6_0_gfx_resume_instance(adev, i);
if (r)
return r;
amdgpu_fence_driver_force_completion(ring);
--
2.50.0
