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> -----Original Message-----
> From: Jesse.Zhang <jesse.zh...@amd.com>
> Sent: Monday, June 2, 2025 11:09 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <alexander.deuc...@amd.com>; Koenig, Christian
> <christian.koe...@amd.com>; Kuehling, Felix <felix.kuehl...@amd.com>; Kim,
> Jonathan <jonathan....@amd.com>; Zhang, Jesse(Jie) <jesse.zh...@amd.com>
> Subject: [PATCH] drm/amdkfd: Move SDMA queue reset capability check to
> node_show
>
> Relocate the per-SDMA queue reset capability check from
> kfd_topology_set_capabilities() to node_show() to ensure we read the
> latest value of sdma.supported_reset after all IP blocks are initialized.
>
> Signed-off-by: Jesse Zhang <jesse.zh...@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index baa2374acdeb..e123952e9a74 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -510,6 +510,10 @@ static ssize_t node_show(struct kobject *kobj, struct
> attribute *attr,
> dev->node_props.capability |=
> HSA_CAP_AQL_QUEUE_DOUBLE_MAP;
>
> + if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0))
> + if (dev->gpu->adev->sdma.supported_reset &
> AMDGPU_RESET_TYPE_PER_QUEUE)
Thanks for the fix.
You can probably squash the nested ifs into a single if with a logical-AND
check on both test conditions.
Please also tag the description with "Fixes:" before submission.
With that addressed:
Reviewed-by: Jonathan Kim <jonathan....@amd.com>
> + dev->node_props.capability2 |=
> HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
> +
> sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_fcompute",
> dev->node_props.max_engine_clk_fcompute);
>
> @@ -2008,8 +2012,6 @@ static void kfd_topology_set_capabilities(struct
> kfd_topology_device *dev)
> if (!amdgpu_sriov_vf(dev->gpu->adev))
> dev->node_props.capability |=
> HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
>
> - if (dev->gpu->adev->sdma.supported_reset &
> AMDGPU_RESET_TYPE_PER_QUEUE)
> - dev->node_props.capability2 |=
> HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
> } else {
> dev->node_props.debug_prop |=
> HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
> HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
> --
> 2.49.0
