[PATCH 05/10] drm/amdgpu/gfx11: adjust ring reset sequences

[Alex Deucher]

Don't clear the ring contents after we issue
a VM reset just write the trailing fence.  GFX
block will reset the work associated with the
vmid and and then continue from where it left off.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 18 ++++++++++--------
 drivers/gpu/drm/amd/amdgpu/nvd.h       |  1 +
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index afd6d59164bfa..5d57dba08717c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5903,6 +5903,7 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
 {
        bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
        bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
+       bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
 
        /* RELEASE_MEM - flush caches, send int */
        amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
@@ -5912,7 +5913,8 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
                                 PACKET3_RELEASE_MEM_GCR_GLM_WB |
                                 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
                                 
PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
-                                PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
+                                PACKET3_RELEASE_MEM_EVENT_INDEX(5) |
+                                (exec ? PACKET3_RELEASE_MEM_EXECUTE_GFX11 : 
0)));
        amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 
1) |
                                 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
 
@@ -6823,19 +6825,19 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring 
*ring, unsigned int vmid)
                        return r;
        }
 
-       r = gfx_v11_0_kgq_init_queue(ring, true);
-       if (r) {
-               dev_err(adev->dev, "failed to init kgq\n");
-               return r;
-       }
-
        r = amdgpu_mes_map_legacy_queue(adev, ring);
        if (r) {
                dev_err(adev->dev, "failed to remap kgq\n");
                return r;
        }
 
-       return amdgpu_ring_test_ring(ring);
+       if (amdgpu_ring_alloc(ring, 8))
+               return -ENOMEM;
+       amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
+                              ring->fence_drv.sync_seq, 
AMDGPU_FENCE_FLAG_EXEC);
+       amdgpu_ring_commit(ring);
+
+       return gfx_v11_0_ring_test_ib(ring, AMDGPU_QUEUE_RESET_TIMEOUT);
 }
 
 static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h
index 56f1bfac0b208..f0c3e3a870541 100644
--- a/drivers/gpu/drm/amd/amdgpu/nvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/nvd.h
@@ -371,6 +371,7 @@
                 * 3 - cache_policy__me_release_mem__bypass
                 */
 #define                PACKET3_RELEASE_MEM_EXECUTE             (1 << 28)
+#define                PACKET3_RELEASE_MEM_EXECUTE_GFX11       (3 << 28)
 
 #define                PACKET3_RELEASE_MEM_DATA_SEL(x)         ((x) << 29)
                /* 0 - discard
-- 
2.49.0