added register to enable vcn ras
Signed-off-by: Mangesh Gadre <mangesh.ga...@amd.com>
Reviewed-by: Stanley.Yang <stanley.y...@amd.com>
---
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h | 2 ++
.../gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
index c4aaa86a95e2..f45155280ff5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
@@ -1067,6 +1067,8 @@
#define regVCN_FEATURES_BASE_IDX
1
#define regUVD_GPUIOV_STATUS
0x0055
#define regUVD_GPUIOV_STATUS_BASE_IDX
1
+#define regUVD_RAS_VCPU_VCODEC_STATUS
0x0057
+#define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX
1
#define regUVD_SCRATCH15
0x005c
#define regUVD_SCRATCH15_BASE_IDX
1
#define regUVD_VERSION
0x005d
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
index bd7242e4e9c6..eb8ff9de5826 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
@@ -5714,6 +5714,12 @@
//UVD_GPUIOV_STATUS
#define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT
0x0
#define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK
0x00000001L
+//UVD_RAS_VCPU_VCODEC_STATUS
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT
0x0
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT
0x1f
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK
0x7FFFFFFFL
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK
0x80000000L
+
//UVD_SCRATCH15
#define UVD_SCRATCH15__SCRATCH15_DATA__SHIFT
0x0
#define UVD_SCRATCH15__SCRATCH15_DATA_MASK
0xFFFFFFFFL
--
2.34.1
