[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Leo Liu <leo....@amd.com>
> -----Original Message-----
> From: Dong, Ruijing <ruijing.d...@amd.com>
> Sent: May 5, 2025 10:46 AM
> To: amd-gfx@lists.freedesktop.org; Jamadar, Saleemkhan
> <saleemkhan.jama...@amd.com>
> Cc: Deucher, Alexander <alexander.deuc...@amd.com>; Koenig, Christian
> <christian.koe...@amd.com>; Liu, Leo <leo....@amd.com>; Dong, Ruijing
> <ruijing.d...@amd.com>
> Subject: [PATCH v2] drm/amdgpu/vcn: using separate VCN1_AON_SOC offset
>
> v1: fix GFX10_ADDR_CONFIG programming for vcn1
> v2: VCN1_AON_SOC_ADDRESS_3_0 offset varies on different
> VCN generations, the issue in vcn4.0.5 is caused by
> a different VCN1_AON_SOC_ADDRESS_3_0 offset.
>
> This patch does the following:
>
> 1. use the same offset for other VCN generations.
> 2. use the vcn4.0.5 speical offset
> 3. update vcn_4_0 and vcn_5_0
>
> Signed-off-by: Ruijing Dong <ruijing.d...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 -
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 2 +-
> 8 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index cdcdae7f71ce..83adf81defc7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -66,7 +66,6 @@
> #define VCN_ENC_CMD_REG_WAIT 0x0000000c
>
> #define VCN_AON_SOC_ADDRESS_2_0 0x1f800
> -#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
> #define VCN_VID_IP_ADDRESS_2_0 0x0
> #define VCN_AON_IP_ADDRESS_2_0 0x30000
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 8e7a36f26e9c..b8d835c9e17e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -39,6 +39,7 @@
>
> #define VCN_VID_SOC_ADDRESS_2_0
> 0x1fa00
> #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
> +#define VCN1_AON_SOC_ADDRESS_3_0
> 0x48000
>
> #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
> #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET
> 0x503
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index d716510b8dd6..3eec1b8feaee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -39,6 +39,7 @@
>
> #define VCN_VID_SOC_ADDRESS_2_0
> 0x1fa00
> #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
> +#define VCN1_AON_SOC_ADDRESS_3_0
> 0x48000
>
> #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
> #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET
> 0x0f
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 22ae1939476f..0b19f0ab4480 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -40,6 +40,7 @@
>
> #define VCN_VID_SOC_ADDRESS_2_0
> 0x1fa00
> #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
> +#define VCN1_AON_SOC_ADDRESS_3_0
> 0x48000
>
> #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
> #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET
> 0x0f
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index c6f6392c1c20..351afec0fc82 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -46,6 +46,7 @@
>
> #define VCN_VID_SOC_ADDRESS_2_0
> 0x1fb00
> #define VCN1_VID_SOC_ADDRESS_3_0
> 0x48300
> +#define VCN1_AON_SOC_ADDRESS_3_0
> 0x48000
>
> #define VCN_HARVEST_MMSCH
> 0
>
> @@ -614,7 +615,7 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
>
> /* VCN global tiling registers */
> WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> - VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev-
> >gfx.config.gb_addr_config, 0, indirect);
> + VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), adev-
> >gfx.config.gb_addr_config, 0, indirect);
> }
>
> /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 139c83bd165e..712e1fba33ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -45,6 +45,7 @@
>
> #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
> #define VCN1_VID_SOC_ADDRESS_3_0 0x48300
> +#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
>
> static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
> SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index a8cfc63713ad..558469744f3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -46,6 +46,7 @@
>
> #define VCN_VID_SOC_ADDRESS_2_0
> 0x1fb00
> #define VCN1_VID_SOC_ADDRESS_3_0
> (0x48300 + 0x38000)
> +#define VCN1_AON_SOC_ADDRESS_3_0
> (0x48000 + 0x38000)
>
> #define VCN_HARVEST_MMSCH
> 0
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index d99d05f42f1d..75c9e7091558 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -533,7 +533,7 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct
> amdgpu_vcn_inst *vinst,
>
> /* VCN global tiling registers */
> WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
> - VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev-
> >gfx.config.gb_addr_config, 0, indirect);
> + VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), adev-
> >gfx.config.gb_addr_config, 0, indirect);
>
> return;
> }
> --
> 2.48.0.rc0.12.gaaf18a9a82
