[Public]
________________________________
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of Alex Deucher
<alexander.deuc...@amd.com>
Sent: Monday, April 28, 2025 5:20 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <alexander.deuc...@amd.com>; Khatri, Sunil
<sunil.kha...@amd.com>; Liang, Prike <prike.li...@amd.com>
Subject: [PATCH 5/8] drm/amdgpu/mes12: add support for setting gang submit
Enable a primary and secondary queue that schedule together.
v2: fix offset of api_status (Prike)
Acked-by: Sunil Khatri <sunil.kha...@amd.com>
Reviewed-by: Prike Liang <prike.li...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 28 ++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index f9f2fbc0a7166..57d8b78210f9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -879,6 +879,33 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
offsetof(union MESAPI__RESET, api_status));
}
+static int mes_v12_0_set_gang_submit(struct amdgpu_mes *mes,
+ struct mes_set_gang_submit_input *input)
+{
+ union MESAPI__SET_GANG_SUBMIT mes_gang_submit_pkt;
+ int pipe;
+
+ memset(&mes_gang_submit_pkt, 0, sizeof(mes_gang_submit_pkt));
+
+ mes_gang_submit_pkt.header.type = MES_API_TYPE_SCHEDULER;
+ mes_gang_submit_pkt.header.opcode = MES_SCH_API_SET_GANG_SUBMIT;
+ mes_gang_submit_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+ mes_gang_submit_pkt.set_gang_submit.gang_context_addr =
+ input->primary_gang_context_addr;
+ mes_gang_submit_pkt.set_gang_submit.slave_gang_context_addr =
+ input->secondary_gang_context_addr;
+
+ if (mes->adev->enable_uni_mes)
+ pipe = AMDGPU_MES_KIQ_PIPE;
+ else
+ pipe = AMDGPU_MES_SCHED_PIPE;
I think this packet should be always submitted to AMDGPU_MES_SCHED_PIPE, same
pipe
as in mes_v12_0_add_hw_queue where the queue is created.
This is because HWS on AMDGPU_MES_KIQ_PIPE does not have the queue information.
+
+ return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
+ &mes_gang_submit_pkt, sizeof(mes_gang_submit_pkt),
+ offsetof(union MESAPI__SET_GANG_SUBMIT, api_status));
+}
+
static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
.add_hw_queue = mes_v12_0_add_hw_queue,
.remove_hw_queue = mes_v12_0_remove_hw_queue,
@@ -888,6 +915,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
.resume_gang = mes_v12_0_resume_gang,
.misc_op = mes_v12_0_misc_op,
.reset_hw_queue = mes_v12_0_reset_hw_queue,
+ .set_gang_submit = mes_v12_0_set_gang_submit,
};
static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
--
2.49.0
