[AMD Official Use Only - AMD Internal Distribution Only]
Tested-by: Mangesh Gadre <mangesh.ga...@amd.com>
>-----Original Message-----
>From: Lazar, Lijo <lijo.la...@amd.com>
>Sent: Friday, April 25, 2025 12:45 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhang, Hawking <hawking.zh...@amd.com>; Deucher, Alexander
><alexander.deuc...@amd.com>; Kamal, Asad <asad.ka...@amd.com>; Gadre,
>Mangesh <mangesh.ga...@amd.com>
>Subject: [PATCH] drm/amdgpu: Fix query order of XGMI v6.4.1 status
>
>Keep the register offsets as per link order for querying XGMI v6.4.1 link
>status.
>
>Signed-off-by: Lijo Lazar <lijo.la...@amd.com>
>
>Fixes: 0666515023cea ("drm/amdgpu: Fix xgmi v6.4.1 link status reporting")
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>index 95231de26cb1..f51ef4cf16e0 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>@@ -297,8 +297,8 @@ static const struct amdgpu_pcs_ras_field
>xgmi3x16_pcs_ras_fields[] = { static u32 xgmi_v6_4_get_link_status(struct
>amdgpu_device *adev, int global_link_num) {
> const u32 smn_xgmi_6_4_pcs_state_hist1[2] = { 0x11a00070, 0x11b00070 };
>- const u32 smn_xgmi_6_4_1_pcs_state_hist1[2] = { 0x11b00070,
>- 0x12100070 };
>+ const u32 smn_xgmi_6_4_1_pcs_state_hist1[2] = { 0x12100070,
>+ 0x11b00070 };
> u32 i, n;
> u64 addr;
>
>--
>2.25.1
