We remap the HDP registers to an open part of the MMIO
aperture. This doesn't seem to work properly on non-X86 systems,
so only remap on X86_64.
Fixes: c9b8dcabb52a ("drm/amdgpu/hdp4.0: do a posting read when flushing HDP")
Fixes: cf424020e040 ("drm/amdgpu/hdp5.0: do a posting read when flushing HDP")
Fixes: f756dbac1ce1 ("drm/amdgpu/hdp5.2: do a posting read when flushing HDP")
Fixes: abe1cbaec6cf ("drm/amdgpu/hdp6.0: do a posting read when flushing HDP")
Fixes: 689275140cb8 ("drm/amdgpu/hdp7.0: do a posting read when flushing HDP")
Reported-by: Alexey Klimov <alexey.kli...@linaro.org>
Link: https://lists.freedesktop.org/archives/amd-gfx/2025-April/123150.html
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4119
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 17 +++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 17 +++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 17 +++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 17 +++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 16 ++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | 16 ++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 17 +++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 17 +++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 17 +++++++++++++----
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 17 +++++++++++++----
10 files changed, 128 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
index 9b4025c39e440..829904b9ea537 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
@@ -32,10 +32,12 @@
static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev)
@@ -437,6 +439,7 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device
*adev)
static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -445,6 +448,12 @@ static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device
*adev)
regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+ regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) <<
2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 04041b398781b..c19cde544f147 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -65,10 +65,12 @@
static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
@@ -552,6 +554,7 @@ static void nbio_v2_3_clear_doorbell_interrupt(struct
amdgpu_device *adev)
static void nbio_v2_3_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -560,6 +563,12 @@ static void nbio_v2_3_set_reg_remap(struct amdgpu_device
*adev)
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) <<
2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index f89e5f40e1a54..0922cc99977e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -30,10 +30,12 @@
static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v4_3_get_rev_id(struct amdgpu_device *adev)
@@ -475,6 +477,7 @@ static void nbio_v4_3_program_aspm(struct amdgpu_device
*adev)
static void nbio_v4_3_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -483,6 +486,12 @@ static void nbio_v4_3_set_reg_remap(struct amdgpu_device
*adev)
regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
<< 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+
regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index e911368c1aeb5..37f99cecff260 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -54,10 +54,12 @@
static void nbio_v6_1_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
@@ -393,6 +395,7 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device
*adev)
static void nbio_v6_1_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -402,6 +405,12 @@ static void nbio_v6_1_set_reg_remap(struct amdgpu_device
*adev)
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1569a1e934ec4..9e69ae0d9dee2 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -34,10 +34,12 @@
static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
@@ -289,6 +291,7 @@ static void nbio_v7_0_init_registers(struct amdgpu_device
*adev)
static void nbio_v7_0_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -297,6 +300,11 @@ static void nbio_v7_0_set_reg_remap(struct amdgpu_device
*adev)
SOC15_REG_OFFSET(NBIO, 0,
mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
index bed5ef4d87889..bbfe17f2d4e32 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
@@ -29,10 +29,12 @@
static void nbio_v7_11_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v7_11_get_rev_id(struct amdgpu_device *adev)
@@ -364,6 +366,7 @@ static void nbio_v7_11_get_clockgating_state(struct
amdgpu_device *adev,
static void nbio_v7_11_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -372,6 +375,11 @@ static void nbio_v7_11_set_reg_remap(struct amdgpu_device
*adev)
SOC15_REG_OFFSET(NBIO, 0,
regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index acc5f363684ad..a27b3341f3982 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -48,10 +48,12 @@
static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
@@ -407,6 +409,7 @@ static void nbio_v7_2_init_registers(struct amdgpu_device
*adev)
static void nbio_v7_2_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -416,6 +419,12 @@ static void nbio_v7_2_set_reg_remap(struct amdgpu_device
*adev)
regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+ regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) <<
2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index d5002ff931d84..2c451953e9792 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -100,10 +100,12 @@ static void nbio_v7_4_query_ras_error_count(struct
amdgpu_device *adev,
static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
@@ -791,6 +793,7 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device
*adev)
static void nbio_v7_4_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -800,6 +803,12 @@ static void nbio_v7_4_set_reg_remap(struct amdgpu_device
*adev)
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
index 2ee60b8746a61..4f9be8a61b657 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
@@ -29,10 +29,12 @@
static void nbio_v7_7_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
@@ -333,6 +335,7 @@ static void nbio_v7_7_get_clockgating_state(struct
amdgpu_device *adev,
static void nbio_v7_7_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -342,6 +345,12 @@ static void nbio_v7_7_set_reg_remap(struct amdgpu_device
*adev)
regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+ regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) <<
2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index a376f072700dc..456a7b3c66c8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -36,10 +36,12 @@
static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
- WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
- adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ if (adev->rmmio_remap.bus_addr) {
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+ }
}
static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)
@@ -487,6 +489,7 @@ static u64 nbio_v7_9_get_pcie_replay_count(struct
amdgpu_device *adev)
static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev)
{
+#ifdef CONFIG_X86_64
if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
adev->rmmio_remap.bus_addr = adev->rmmio_base +
MMIO_REG_HOLE_OFFSET;
@@ -498,6 +501,12 @@ static void nbio_v7_9_set_reg_remap(struct amdgpu_device
*adev)
<< 2;
adev->rmmio_remap.bus_addr = 0;
}
+#else
+ adev->rmmio_remap.reg_offset =
+ SOC15_REG_OFFSET(NBIO, 0,
+
regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+#endif
}
const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
--
2.49.0
