Some GC registers are duplicated across multiple instances of GC offset
files. This commit creates a new file named gc_common_offset.h that
centralizes some common registers in a single file. Aside from
eliminating multiple duplications, this approach also avoids including
specific registers in generic files (e.g., amdgpu_gfx) and reduces the
number of includes.
Signed-off-by: Rodrigo Siqueira <sique...@igalia.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 +++-
.../gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h | 2 --
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 2 --
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h | 2 --
.../gpu/drm/amd/include/asic_reg/gc/gc_common_offset.h | 9 +++++++++
14 files changed, 13 insertions(+), 23 deletions(-)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_common_offset.h
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a1e3bb43babc..9f92acfdf00c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -32,6 +32,7 @@
#include "nv.h"
#include "nvd.h"
+#include "gc/gc_common_offset.h"
#include "gc/gc_10_1_0_offset.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "smuio/smuio_11_0_0_offset.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 58b10a72c0c9..2aea229ac4bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -33,6 +33,8 @@
#include "soc21.h"
#include "nvd.h"
+#include "gc/gc_common_offset.h"
+
#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
#include "smuio/smuio_13_0_6_offset.h"
@@ -3565,7 +3567,7 @@ static int gfx_v11_0_cp_gfx_start(struct amdgpu_device
*adev)
}
ctx_reg_offset =
- SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) -
PACKET3_SET_CONTEXT_REG_START;
+ SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) -
PACKET3_SET_CONTEXT_REG_START;
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
amdgpu_ring_write(ring, ctx_reg_offset);
amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 4c8e7fdb6976..1e92f71f12b8 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -5974,8 +5974,6 @@
#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define mmPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define mmPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define mmCP_PERFMON_CNTX_CNTL
0x00d8
#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define mmCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 5e15ac14b63c..555a3bc26614 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -5603,8 +5603,6 @@
#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define mmPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define mmPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define mmCP_PERFMON_CNTX_CNTL
0x00d8
#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define mmCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
index a3bcdf632066..b82c72d27cf9 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
@@ -5393,8 +5393,6 @@
#define regPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define regPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define regPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define regCP_PERFMON_CNTX_CNTL
0x00d8
#define regCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define regCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
index 56e00252bff8..82a795135f87 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_offset.h
@@ -5673,8 +5673,6 @@
#define regPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define regPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define regPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define regCP_PERFMON_CNTX_CNTL
0x00d8
#define regCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define regCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
index d6c02cf815be..bf61fc0d3edd 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
@@ -4204,8 +4204,6 @@
#define regPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define regPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define regPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define regCP_PERFMON_CNTX_CNTL
0x00d8
#define regCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define regCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
index 645d10bfbc79..d0df8d0df4e3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h
@@ -8404,8 +8404,6 @@
#define regPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define regPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define regPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define regCB_CP_PIPEID
0x00d9
#define regCB_CP_PIPEID_BASE_IDX
1
#define regCB_CP_VMID
0x00da
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index 12d451e5475b..d5c31df4cea7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -3584,8 +3584,6 @@
#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define mmPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define mmPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define mmCP_PERFMON_CNTX_CNTL
0x00d8
#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define mmCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index d17d1e622e4f..a7d476b6c8e3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -3814,8 +3814,6 @@
#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define mmPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define mmPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define mmCP_PERFMON_CNTX_CNTL
0x00d8
#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define mmCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
index c30720277912..fc5c7abb35e7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h
@@ -3764,8 +3764,6 @@
#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define mmPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define mmPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define mmCP_PERFMON_CNTX_CNTL
0x00d8
#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define mmCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
index 1a8a6a350789..e13fb8137820 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
@@ -1755,8 +1755,6 @@
#define regPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define regPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define regPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define regCP_PERFMON_CNTX_CNTL
0x00d8
#define regCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define regCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
index 393963502b7a..845dbbbfd567 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
@@ -3995,8 +3995,6 @@
#define regPA_SC_RASTER_CONFIG_1_BASE_IDX
1
#define regPA_SC_SCREEN_EXTENT_CONTROL
0x00d6
#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX
1
-#define regPA_SC_TILE_STEERING_OVERRIDE
0x00d7
-#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
#define regCP_PERFMON_CNTX_CNTL
0x00d8
#define regCP_PERFMON_CNTX_CNTL_BASE_IDX
1
#define regCP_PIPEID
0x00d9
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_common_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_common_offset.h
new file mode 100644
index 000000000000..1f7c5f597c05
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_common_offset.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: MIT */
+
+#ifndef _gc_gc_common_offset
+#define _gc_gc_common_offset
+
+#define mmPA_SC_TILE_STEERING_OVERRIDE
0x00d7
+#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX
1
+
+#endif
--
2.49.0
