[Public]
Reviewed-by: Kent Russell <kent.russ...@amd.com>
> -----Original Message-----
> From: Cornwall, Jay <jay.cornw...@amd.com>
> Sent: Friday, March 28, 2025 12:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Cornwall, Jay <jay.cornw...@amd.com>; Russell, Kent
> <kent.russ...@amd.com>
> Subject: [PATCH] Revert "drm/amdgpu: Increase KIQ invalidate_tlbs timeout"
>
> This reverts commit fdb90033846e2f23dfaaa01dc47fec7b94704d0e.
>
> Reportedly causing unknown issue in memory management code:
>
> [ 128.047288] amdgpu 0000:65:00.0: amdgpu: Failed to map peer:0000:46:00.0
> mem_domain:2
> [...]
> [ 137.815340] WARNING: CPU: 81 PID: 1006 at drivers/gpu/drm/ttm/ttm_bo.c:613
> ttm_bo_unpin+0x7e/0x90 [ttm]
>
> Signed-off-by: Jay Cornwall <jay.cornw...@amd.com>
> Cc: Kent Russell <kent.russ...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 ++++------------
> 2 files changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3cdb5f8325aa..ffca74a476da 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -356,6 +356,7 @@ enum amdgpu_kiq_irq {
> AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
> AMDGPU_CP_KIQ_IRQ_LAST
> };
> +#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
> #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
> #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
> #define MAX_KIQ_REG_TRY 1000
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index c46e36a0cd9c..464625282872 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -699,10 +699,12 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct
> amdgpu_device *adev, uint16_t pasid,
> uint32_t flush_type, bool all_hub,
> uint32_t inst)
> {
> + u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT :
> + adev->usec_timeout;
> struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
> unsigned int ndw;
> - int r, cnt = 0;
> + int r;
> uint32_t seq;
>
> /*
> @@ -759,17 +761,7 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct
> amdgpu_device *adev, uint16_t pasid,
>
> amdgpu_ring_commit(ring);
> spin_unlock(&adev->gfx.kiq[inst].ring_lock);
> -
> - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> -
> - might_sleep();
> - while (r < 1 && cnt++ < MAX_KIQ_REG_TRY &&
> - !amdgpu_reset_pending(adev->reset_domain)) {
> - msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
> - r = amdgpu_fence_wait_polling(ring, seq,
> MAX_KIQ_REG_WAIT);
> - }
> -
> - if (cnt > MAX_KIQ_REG_TRY) {
> + if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) {
> dev_err(adev->dev, "timeout waiting for kiq fence\n");
> r = -ETIME;
> }
> --
> 2.34.1
