[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Tao Zhou <tao.zh...@amd.com>
> -----Original Message----- > From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Lijo Lazar > Sent: Monday, March 24, 2025 3:59 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking <hawking.zh...@amd.com>; Deucher, Alexander > <alexander.deuc...@amd.com> > Subject: [PATCH] drm/amdgpu: Add NPS2 to DPX compatible mode > > Compute partition DPX is possible in NPS2 mode. Update the compatible modes > for > DPX. > > Signed-off-by: Lijo Lazar <lijo.la...@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > index 3c07517be09a..ae071985f26e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c > @@ -473,7 +473,8 @@ static int aqua_vanjaram_get_xcp_res_info(struct > amdgpu_xcp_mgr *xcp_mgr, > break; > case AMDGPU_DPX_PARTITION_MODE: > num_xcp = 2; > - nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); > + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | > + BIT(AMDGPU_NPS2_PARTITION_MODE); > break; > case AMDGPU_TPX_PARTITION_MODE: > num_xcp = 3; > -- > 2.25.1
