From: Mario Limonciello <mario.limoncie...@amd.com>

Several other ASICs allow printing OD SCLK levels without setting DPM
control to manual.  When OD is disabled it will show the range the
hardware supports. When OD is enabled it will show what values have been
programmed. Adjust Renoir to work the same.

Reported-by: Vicki Pfau <v...@endrift.com>
Signed-off-by: Mario Limonciello <mario.limoncie...@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c   | 36 +++++++++----------
 1 file changed, 16 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 37d82a71a2d7c..93275ff2ca692 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -510,28 +510,24 @@ static int renoir_print_clk_levels(struct smu_context 
*smu,
 
        switch (clk_type) {
        case SMU_OD_RANGE:
-               if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       ret = smu_cmn_send_smc_msg_with_param(smu,
-                                               SMU_MSG_GetMinGfxclkFrequency,
-                                               0, &min);
-                       if (ret)
-                               return ret;
-                       ret = smu_cmn_send_smc_msg_with_param(smu,
-                                               SMU_MSG_GetMaxGfxclkFrequency,
-                                               0, &max);
-                       if (ret)
-                               return ret;
-                       size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: 
%10uMhz %10uMhz\n", min, max);
-               }
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                       SMU_MSG_GetMinGfxclkFrequency,
+                                       0, &min);
+               if (ret)
+                       return ret;
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                       SMU_MSG_GetMaxGfxclkFrequency,
+                                       0, &max);
+               if (ret)
+                       return ret;
+               size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: %10uMhz 
%10uMhz\n", min, max);
                break;
        case SMU_OD_SCLK:
-               if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       min = (smu->gfx_actual_hard_min_freq > 0) ? 
smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
-                       max = (smu->gfx_actual_soft_max_freq > 0) ? 
smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
-                       size += sysfs_emit_at(buf, size, "OD_SCLK\n");
-                       size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min);
-                       size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max);
-               }
+               min = (smu->gfx_actual_hard_min_freq > 0) ? 
smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
+               max = (smu->gfx_actual_soft_max_freq > 0) ? 
smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
+               size += sysfs_emit_at(buf, size, "OD_SCLK\n");
+               size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min);
+               size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max);
                break;
        case SMU_GFXCLK:
        case SMU_SCLK:
-- 
2.43.0

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