This is not in device_info, but it'll do.
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Marek
On Mon, Mar 17, 2025 at 5:38 PM Alex Deucher <alexander.deuc...@amd.com>
wrote:
> Add an INFO query to check if user queues are supported.
>
> v2: switch to a mask of IPs (Marek)
>
> Cc: marek.ol...@amd.com
> Cc: prike.li...@amd.com
> Cc: sunil.kha...@amd.com
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 13 +++++++++++++
> include/uapi/drm/amdgpu_drm.h | 8 ++++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 3b7dfd56ccd0e..1d683c0487697 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -1340,6 +1340,19 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> return -EINVAL;
> }
> }
> + case AMDGPU_INFO_UQ_SUPPORTED: {
> + struct drm_amdgpu_info_uq_supported uq_supported = {};
> +
> + if (adev->userq_funcs[AMDGPU_HW_IP_GFX])
> + uq_supported.supported |= (1 << AMDGPU_HW_IP_GFX);
> + if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE])
> + uq_supported.supported |= (1 <<
> AMDGPU_HW_IP_COMPUTE);
> + if (adev->userq_funcs[AMDGPU_HW_IP_DMA])
> + uq_supported.supported |= (1 << AMDGPU_HW_IP_DMA);
> + ret = copy_to_user(out, &uq_supported,
> + min((size_t)size,
> sizeof(uq_supported))) ? -EFAULT : 0;
> + return 0;
> + }
> default:
> DRM_DEBUG_KMS("Invalid request %d\n", info->query);
> return -EINVAL;
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 5dbd9037afe75..4b64e91002c05 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -1195,6 +1195,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
> #define AMDGPU_INFO_GPUVM_FAULT 0x23
> /* query FW object size and alignment */
> #define AMDGPU_INFO_UQ_FW_AREAS 0x24
> +/* query if user queues are supported */
> +#define AMDGPU_INFO_UQ_SUPPORTED 0x25
>
> #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
> #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
> @@ -1572,6 +1574,12 @@ struct drm_amdgpu_info_uq_metadata {
> };
> };
>
> +struct drm_amdgpu_info_uq_supported {
> + /** returns a mask for each IP type (1 << AMDGPU_HW_IP_*) */
> + __u32 supported;
> + __u32 pad;
> +};
> +
> /*
> * Supported GPU families
> */
> --
> 2.48.1
>
>
