On Sat, Mar 8, 2025 at 7:32 PM Alexandre Demers
<alexandre.f.dem...@gmail.com> wrote:
>
> On Thu, Mar 6, 2025 at 10:19 AM Alex Deucher <alexdeuc...@gmail.com> wrote:
> >
> > On Wed, Mar 5, 2025 at 9:08 PM Alexandre Demers
> > <alexandre.f.dem...@gmail.com> wrote:
> > >
> > > For coherence with DCE8 et DCE10, add or move some values under sid.h.
> > >
> > > Signed-off-by: Alexandre Demers <alexandre.f.dem...@gmail.com>
> >
> > This change doesn't build. Please adjust the order of the patches as
> > needed to make sure they all build.
> >
> > Alex
>
> Yeah, adding sid.h should probably be at the end, once all changes are
> made. I'll look at it.
>
> Thanks for noticing.
> Alexandre
V4 is sent, it compiles at each commit. I did not include the DCE8
patch (4/4) since it was accepted in V3 and applied.
Alexandre
> >
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 63 ++++++++++++++-------------
> > > drivers/gpu/drm/amd/amdgpu/si_enums.h | 7 ---
> > > drivers/gpu/drm/amd/amdgpu/sid.h | 29 +++++++++---
> > > 3 files changed, 55 insertions(+), 44 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > index a72fd7220081..185401d66961 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > > @@ -32,6 +32,7 @@
> > > #include "amdgpu.h"
> > > #include "amdgpu_pm.h"
> > > #include "amdgpu_i2c.h"
> > > +#include "sid.h"
> > > #include "atom.h"
> > > #include "amdgpu_atombios.h"
> > > #include "atombios_crtc.h"
> > > @@ -59,31 +60,31 @@ static void dce_v6_0_set_irq_funcs(struct
> > > amdgpu_device *adev);
> > >
> > > static const u32 crtc_offsets[6] =
> > > {
> > > - SI_CRTC0_REGISTER_OFFSET,
> > > - SI_CRTC1_REGISTER_OFFSET,
> > > - SI_CRTC2_REGISTER_OFFSET,
> > > - SI_CRTC3_REGISTER_OFFSET,
> > > - SI_CRTC4_REGISTER_OFFSET,
> > > - SI_CRTC5_REGISTER_OFFSET
> > > + CRTC0_REGISTER_OFFSET,
> > > + CRTC1_REGISTER_OFFSET,
> > > + CRTC2_REGISTER_OFFSET,
> > > + CRTC3_REGISTER_OFFSET,
> > > + CRTC4_REGISTER_OFFSET,
> > > + CRTC5_REGISTER_OFFSET
> > > };
> > >
> > > static const u32 hpd_offsets[] =
> > > {
> > > - mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
> > > - mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
> > > - mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
> > > - mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
> > > - mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
> > > - mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
> > > + HPD0_REGISTER_OFFSET,
> > > + HPD1_REGISTER_OFFSET,
> > > + HPD2_REGISTER_OFFSET,
> > > + HPD3_REGISTER_OFFSET,
> > > + HPD4_REGISTER_OFFSET,
> > > + HPD5_REGISTER_OFFSET
> > > };
> > >
> > > static const uint32_t dig_offsets[] = {
> > > - SI_CRTC0_REGISTER_OFFSET,
> > > - SI_CRTC1_REGISTER_OFFSET,
> > > - SI_CRTC2_REGISTER_OFFSET,
> > > - SI_CRTC3_REGISTER_OFFSET,
> > > - SI_CRTC4_REGISTER_OFFSET,
> > > - SI_CRTC5_REGISTER_OFFSET,
> > > + CRTC0_REGISTER_OFFSET,
> > > + CRTC1_REGISTER_OFFSET,
> > > + CRTC2_REGISTER_OFFSET,
> > > + CRTC3_REGISTER_OFFSET,
> > > + CRTC4_REGISTER_OFFSET,
> > > + CRTC5_REGISTER_OFFSET,
> > > (0x13830 - 0x7030) >> 2,
> > > };
> > >
> > > @@ -1359,13 +1360,13 @@ static void dce_v6_0_audio_enable(struct
> > > amdgpu_device *adev,
> > >
> > > static const u32 pin_offsets[7] =
> > > {
> > > - (0x1780 - 0x1780),
> > > - (0x1786 - 0x1780),
> > > - (0x178c - 0x1780),
> > > - (0x1792 - 0x1780),
> > > - (0x1798 - 0x1780),
> > > - (0x179d - 0x1780),
> > > - (0x17a4 - 0x1780),
> > > + AUD0_REGISTER_OFFSET,
> > > + AUD1_REGISTER_OFFSET,
> > > + AUD2_REGISTER_OFFSET,
> > > + AUD3_REGISTER_OFFSET,
> > > + AUD4_REGISTER_OFFSET,
> > > + AUD5_REGISTER_OFFSET,
> > > + AUD6_REGISTER_OFFSET,
> > > };
> > >
> > > static int dce_v6_0_audio_init(struct amdgpu_device *adev)
> > > @@ -2876,22 +2877,22 @@ static void
> > > dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
> > >
> > > switch (crtc) {
> > > case 0:
> > > - reg_block = SI_CRTC0_REGISTER_OFFSET;
> > > + reg_block = CRTC0_REGISTER_OFFSET;
> > > break;
> > > case 1:
> > > - reg_block = SI_CRTC1_REGISTER_OFFSET;
> > > + reg_block = CRTC1_REGISTER_OFFSET;
> > > break;
> > > case 2:
> > > - reg_block = SI_CRTC2_REGISTER_OFFSET;
> > > + reg_block = CRTC2_REGISTER_OFFSET;
> > > break;
> > > case 3:
> > > - reg_block = SI_CRTC3_REGISTER_OFFSET;
> > > + reg_block = CRTC3_REGISTER_OFFSET;
> > > break;
> > > case 4:
> > > - reg_block = SI_CRTC4_REGISTER_OFFSET;
> > > + reg_block = CRTC4_REGISTER_OFFSET;
> > > break;
> > > case 5:
> > > - reg_block = SI_CRTC5_REGISTER_OFFSET;
> > > + reg_block = CRTC5_REGISTER_OFFSET;
> > > break;
> > > default:
> > > DRM_DEBUG("invalid crtc %d\n", crtc);
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h
> > > b/drivers/gpu/drm/amd/amdgpu/si_enums.h
> > > index 4e935baa7b91..cdf8eebaa392 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
> > > @@ -121,13 +121,6 @@
> > > #define CURSOR_UPDATE_LOCK (1 << 16)
> > > #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
> > >
> > > -#define SI_CRTC0_REGISTER_OFFSET 0
> > > -#define SI_CRTC1_REGISTER_OFFSET 0x300
> > > -#define SI_CRTC2_REGISTER_OFFSET 0x2600
> > > -#define SI_CRTC3_REGISTER_OFFSET 0x2900
> > > -#define SI_CRTC4_REGISTER_OFFSET 0x2c00
> > > -#define SI_CRTC5_REGISTER_OFFSET 0x2f00
> > > -
> > > #define DMA0_REGISTER_OFFSET 0x000
> > > #define DMA1_REGISTER_OFFSET 0x200
> > > #define ES_AND_GS_AUTO 3
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h
> > > b/drivers/gpu/drm/amd/amdgpu/sid.h
> > > index 9a39cbfe6db9..32a4e7d450c6 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/sid.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/sid.h
> > > @@ -1991,12 +1991,29 @@
> > >
> > > //#dce stupp
> > > /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
> > > -#define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/4
> > > -#define SI_CRTC1_REGISTER_OFFSET 0x300 //(0x79f0 -
> > > 0x6df0)/4
> > > -#define SI_CRTC2_REGISTER_OFFSET 0x2600 //(0x105f0 -
> > > 0x6df0)/4
> > > -#define SI_CRTC3_REGISTER_OFFSET 0x2900 //(0x111f0 -
> > > 0x6df0)/4
> > > -#define SI_CRTC4_REGISTER_OFFSET 0x2c00 //(0x11df0 -
> > > 0x6df0)/4
> > > -#define SI_CRTC5_REGISTER_OFFSET 0x2f00 //(0x129f0 -
> > > 0x6df0)/4
> > > +#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
> > > //(0x6df0 - 0x6df0)/4
> > > +#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
> > > //(0x79f0 - 0x6df0)/4
> > > +#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c)
> > > //(0x105f0 - 0x6df0)/4
> > > +#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c)
> > > //(0x111f0 - 0x6df0)/4
> > > +#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c)
> > > //(0x11df0 - 0x6df0)/4
> > > +#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c)
> > > //(0x129f0 - 0x6df0)/4
> > > +
> > > +/* hpd instance offsets */
> > > +#define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
> > > +#define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
> > > +#define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
> > > +#define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
> > > +#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
> > > +#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
> > > +
> > > +/* audio endpt instance offsets */
> > > +#define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
> > > +#define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
> > > +#define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
> > > +#define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
> > > +#define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
> > > +#define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
> > > +#define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
> > >
> > > #define CURSOR_WIDTH 64
> > > #define CURSOR_HEIGHT 64
> > > --
> > > 2.48.1
> > >
