[PATCH 13/22] drm/amd/display: dml2 soc dscclk use DPM table clk setting.

[Tom Chung]

From: Charlene Liu <charlene....@amd.com>

[why & how]
The dml2 will calculate the minimum required clocks.
Use DPM table clk setting for dml2 soc dscclk.

Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Signed-off-by: Charlene Liu <charlene....@amd.com>
Signed-off-by: Tom Chung <chiahsuan.ch...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 2061d43b92e1..70c39df62533 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -590,11 +590,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, 
const struct dc *in_dc,
                        p->out_states->state_array[i].dtbclk_mhz = 
max_dtbclk_mhz;
                        p->out_states->state_array[i].phyclk_mhz = 
max_phyclk_mhz;
 
-                       p->out_states->state_array[i].dscclk_mhz = 
max_dispclk_mhz / 3.0;
                        p->out_states->state_array[i].phyclk_mhz = 
max_phyclk_mhz;
                        p->out_states->state_array[i].dtbclk_mhz = 
max_dtbclk_mhz;
 
                        /* Dependent states. */
+                       p->out_states->state_array[i].dscclk_mhz = 
p->in_states->state_array[i].dscclk_mhz;
                        p->out_states->state_array[i].dram_speed_mts = 
p->in_states->state_array[i].dram_speed_mts;
                        p->out_states->state_array[i].fabricclk_mhz = 
p->in_states->state_array[i].fabricclk_mhz;
                        p->out_states->state_array[i].socclk_mhz = 
p->in_states->state_array[i].socclk_mhz;
-- 
2.34.1