[PATCH 1/2] drm/amdgpu: retire ip init code specific for A0 rev

[Shiwu Zhang]

For aqua_vanjaram, A0 HW is retired so remove the code
specific for it in gfx ip init.

Signed-off-by: Shiwu Zhang <shiwu.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 36505d56ab86..2705f0cdd6da 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -351,18 +351,7 @@ static void gfx_v9_4_3_init_golden_registers(struct 
amdgpu_device *adev)
 
                WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,
                             GOLDEN_GB_ADDR_CONFIG);
-               if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 
{
-                       WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 
SPARE, 0x1);
-               } else {
-                       /* Golden settings applied by driver for ASIC with 
rev_id 0 */
-                       if (adev->rev_id == 0) {
-                               WREG32_FIELD15_PREREG(GC, dev_inst, 
TCP_UTCL1_CNTL1,
-                                                     REDUCE_FIFO_DEPTH_BY_2, 
2);
-                       } else {
-                               WREG32_FIELD15_PREREG(GC, dev_inst, 
TCP_UTCL1_CNTL2,
-                                                     SPARE, 0x1);
-                       }
-               }
+               WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 
0x1);
        }
 }
 
-- 
2.34.1