[PATCH 1/2] drm/amdgpu: Use the right struct for VCN v5.0.1

[Lijo Lazar]

VCN IP versions >= 5.0 uses VCN5 fw shared struct.

Signed-off-by: Lijo Lazar <lijo.la...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
index d29e8d685194..7ef83c9346e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
@@ -153,7 +153,7 @@ static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block 
*ip_block)
 
        if (drm_dev_enter(adev_to_drm(adev), &idx)) {
                for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-                       volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+                       volatile struct amdgpu_vcn5_fw_shared *fw_shared;
 
                        fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
                        fw_shared->present_flag_0 = 0;
@@ -341,7 +341,7 @@ static void vcn_v5_0_1_mc_resume(struct amdgpu_vcn_inst 
*vinst)
                upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
        WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
        WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0,
-               AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
+               AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)));
 }
 
 /**
@@ -451,7 +451,7 @@ static void vcn_v5_0_1_mc_resume_dpg_mode(struct 
amdgpu_vcn_inst *vinst,
                VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
        WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
                VCN, 0, regUVD_VCPU_NONCACHE_SIZE0),
-               AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, 
indirect);
+               AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, 
indirect);
 
        /* VCN global tiling registers */
        WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
@@ -493,7 +493,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst 
*vinst,
 {
        struct amdgpu_device *adev = vinst->adev;
        int inst_idx = vinst->inst;
-       volatile struct amdgpu_vcn4_fw_shared *fw_shared =
+       volatile struct amdgpu_vcn5_fw_shared *fw_shared =
                adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
        struct amdgpu_ring *ring;
        int vcn_inst;
@@ -602,7 +602,7 @@ static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst)
 {
        struct amdgpu_device *adev = vinst->adev;
        int i = vinst->inst;
-       volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+       volatile struct amdgpu_vcn5_fw_shared *fw_shared;
        struct amdgpu_ring *ring;
        uint32_t tmp;
        int j, k, r, vcn_inst;
@@ -780,7 +780,7 @@ static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst)
 {
        struct amdgpu_device *adev = vinst->adev;
        int i = vinst->inst;
-       volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+       volatile struct amdgpu_vcn5_fw_shared *fw_shared;
        uint32_t tmp;
        int r = 0, vcn_inst;
 
-- 
2.25.1