On 2/25/2025 2:13 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com" <jesse.zh...@amd.com>
>
> This commit updates the VM flush implementation for the SDMA engine.
>
> - Added a new function `sdma_v4_4_2_get_invalidate_req` to construct the
> VM_INVALIDATE_ENG0_REQ
> register value for the specified VMID and flush type. This function ensures
> that all relevant
> page table cache levels (L1 PTEs, L2 PTEs, and L2 PDEs) are invalidated.
>
> - Modified the `sdma_v4_4_2_ring_emit_vm_flush` function to use the new
> `sdma_v4_4_2_get_invalidate_req`
> function. The updated function emits the necessary register writes and
> waits to perform a VM flush
> for the specified VMID. It updates the PTB address registers and issues a
> VM invalidation request
> using the specified VM invalidation engine.
>
> - Included the necessary header file `gc/gc_9_0_sh_mask.h` to provide access
> to the required register
> definitions.
>
> Suggested-by: Lijo Lazar <lijo.la...@amd.com>
> Signed-off-by: Jesse Zhang <jesse.zh...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 66 ++++++++++++++++++++----
> 1 file changed, 57 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index ba43c8f46f45..f9cec50ce54e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -31,6 +31,7 @@
> #include "amdgpu_ucode.h"
> #include "amdgpu_trace.h"
> #include "amdgpu_reset.h"
> +#include "gc/gc_9_0_sh_mask.h"
>
> #include "sdma/sdma_4_4_2_offset.h"
> #include "sdma/sdma_4_4_2_sh_mask.h"
> @@ -1292,21 +1293,68 @@ static void
> sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
> seq, 0xffffffff, 4);
> }
>
> -
> -/**
> - * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
> +/*
> + * sdma_v4_4_2_get_invalidate_req - Construct the VM_INVALIDATE_ENG0_REQ
> register value
> + * @vmid: The VMID to invalidate
> + * @flush_type: The type of flush (0 = legacy, 1 = lightweight, 2 =
> heavyweight)
> *
> - * @ring: amdgpu_ring pointer
> - * @vmid: vmid number to use
> - * @pd_addr: address
> + * This function constructs the VM_INVALIDATE_ENG0_REQ register value for
> the specified VMID
> + * and flush type. It ensures that all relevant page table cache levels (L1
> PTEs, L2 PTEs, and
> + * L2 PDEs) are invalidated.
> + */
> +static uint32_t sdma_v4_4_2_get_invalidate_req(unsigned int vmid,
> + uint32_t flush_type)
> +{
> + u32 req = 0;
> +
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> + PER_VMID_INVALIDATE_REQ, 1 << vmid);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE,
> flush_type);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
> + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
> + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
> +
> + return req;
> +}
> +
> +/*
> + * sdma_v4_4_2_ring_emit_vm_flush - Emit VM flush commands for SDMA
> + * @ring: The SDMA ring
> + * @vmid: The VMID to flush
> + * @pd_addr: The page directory address
> *
> - * Update the page table base and flush the VM TLB
> - * using sDMA.
> + * This function emits the necessary register writes and waits to perform a
> VM flush for the
> + * specified VMID. It updates the PTB address registers and issues a VM
> invalidation request
> + * using the specified VM invalidation engine.
> */
> static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> - amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
> + struct amdgpu_device *adev = ring->adev;
> + struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
> + uint32_t req = sdma_v4_4_2_get_invalidate_req(vmid, 0);
> + unsigned int eng = ring->vm_inv_eng;
> +
> + /* Update the PTB address for the specified VMID */
> + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
> + (hub->ctx_addr_distance * vmid),
> + lower_32_bits(pd_addr));
> +
> + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
> + (hub->ctx_addr_distance * vmid),
> + upper_32_bits(pd_addr));
> +
> + /* Issue the VM invalidation request and wait for acknowledgment */
> + amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
> + hub->eng_distance * eng,
> + hub->vm_inv_eng0_ack +
> + hub->eng_distance * eng,
> + req, 1 << vmid);
Sorry, this is not how it is. VM_INVALIDATE a totally different packet.
Instead of wreg/reg_wait, it will be using something like
emit_invalidate(). The packet needs to be filled with invalidate engine
details. You may refer the packet spec for more details.
Thanks,
Lijo
> +
> }
>
> static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
