[PATCH 1/3] drm/amdgpu: Save nps to eeprom

[ganglxie]

nps info saved together with bad page makes bad page parsing more efficient

Signed-off-by: ganglxie <gangl...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 8 ++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h        | 7 +++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 83b54efcaa87..87fcdda3ec61 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -852,6 +852,7 @@ int amdgpu_ras_eeprom_append(struct 
amdgpu_ras_eeprom_control *control,
 {
        struct amdgpu_device *adev = to_amdgpu_device(control);
        int res, i;
+       uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;
 
        if (!__is_ras_eeprom_supported(adev))
                return 0;
@@ -865,9 +866,12 @@ int amdgpu_ras_eeprom_append(struct 
amdgpu_ras_eeprom_control *control,
                return -EINVAL;
        }
 
+       if (adev->gmc.gmc_funcs->query_mem_partition_mode)
+               nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
+
        /* set the new channel index flag */
        for (i = 0; i < num; i++)
-               record[i].retired_page |= UMC_CHANNEL_IDX_V2;
+               record[i].retired_page |= (nps << UMC_NPS_SHIFT);
 
        mutex_lock(&control->ras_tbl_mutex);
 
@@ -881,7 +885,7 @@ int amdgpu_ras_eeprom_append(struct 
amdgpu_ras_eeprom_control *control,
 
        /* clear channel index flag, the flag is only saved on eeprom */
        for (i = 0; i < num; i++)
-               record[i].retired_page &= ~UMC_CHANNEL_IDX_V2;
+               record[i].retired_page &= ~(nps << UMC_NPS_SHIFT);
 
        return res;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index a4a7e61817aa..857693bcd8d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -71,6 +71,13 @@
  */
 #define UMC_CHANNEL_IDX_V2     BIT_ULL(47)
 
+/*
+ * save nps value to eeprom_table_record.retired_page[47:40],
+ * the channel index flag above will be retired.
+ */
+#define UMC_NPS_SHIFT 40
+#define UMC_NPS_MASK 0xffULL
+
 typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
                        uint32_t umc_inst, uint32_t ch_inst, void *data);
 
-- 
2.34.1