On 2/6/2025 16:27, Russell, Kent wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Ping (plus Jay)
Sorry, I'd need the whole patch chain to review.
As a general comment CP_IQ_WAIT_TIME2.QUE_SLEEP is tangential to
SCH_WAVE. I'm not sure it's useful to tie these together.
SCH_WAVE is lowered when a debugger attaches to reduce context switching
latency, which it triggers at a high frequency. Higher latency (the
default) is desirable in normal use to allow short-running wavefronts to
complete rather than taking the slow save path.
QUE_SLEEP controls the interval between checks for unmet conditions
(e.g. WAIT_REG_MEM or CUs fully occupied). On contemporary ASICs it's
best to minimize this by default. The cost is additional bandwidth
consumed by CP when polling memory, but it's not substantial.
