Implement the GFX11 compute pipe reset. As the GFX11 CPFW
still hasn't fully supported pipe reset yet, therefore
disable the KCQ pipe reset temporarily.
Signed-off-by: Prike Liang <prike.li...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 139 ++++++++++++++++++++++++-
1 file changed, 136 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 395872bb1401..39fd3ce67ec9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -66,6 +66,7 @@
#define regPC_CONFIG_CNTL_1_BASE_IDX 1
static uint32_t me_fw_start_pc;
+static uint32_t mec_fw_start_pc;
MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
@@ -2937,6 +2938,7 @@ static void gfx_v11_0_config_gfx_rs64(struct
amdgpu_device *adev)
/* cache the firmware start PC */
me_fw_start_pc = RREG32(SOC15_REG_OFFSET(GC, 0,
regCP_GFX_RS64_INSTR_PNTR1));
+ mec_fw_start_pc = RREG32(SOC15_REG_OFFSET(GC, 0,
regCP_MEC_RS64_INSTR_PNTR));
}
static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
@@ -3812,7 +3814,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct
amdgpu_device *adev)
le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
-
+ mec_fw_start_pc = RREG32(SOC15_REG_OFFSET(GC, 0,
regCP_MEC1_INSTR_PNTR));
return 0;
}
@@ -6764,6 +6766,135 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring
*ring, unsigned int vmid)
return amdgpu_ring_test_ring(ring);
}
+static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring)
+{
+
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t reset_pipe = 0, clean_pipe = 0;
+ int r;
+
+ if (!gfx_v11_pipe_reset_support(adev))
+ return -EOPNOTSUPP;
+
+ gfx_v11_0_set_safe_mode(adev, 0);
+ mutex_lock(&adev->srbm_mutex);
+ soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+
+ reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
+ clean_pipe = reset_pipe;
+
+ if (adev->gfx.rs64_enable) {
+
+ switch (ring->pipe) {
+ case 0:
+ reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE0_RESET, 1);
+ clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE0_RESET, 0);
+ break;
+ case 1:
+ reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE1_RESET, 1);
+ clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE1_RESET, 0);
+ break;
+ case 2:
+ reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE2_RESET, 1);
+ clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE2_RESET, 0);
+ break;
+ case 3:
+ reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE3_RESET, 1);
+ clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
+ MEC_PIPE3_RESET, 0);
+ break;
+ default:
+ break;
+ }
+ WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);
+ WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);
+ r = RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) -
mec_fw_start_pc;
+ } else {
+ if (ring->me == 1) {
+ switch (ring->pipe) {
+ case 0:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE0_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE0_RESET,
0);
+ break;
+ case 1:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE1_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE1_RESET,
0);
+ break;
+ case 2:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE2_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE2_RESET,
0);
+ break;
+ case 3:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE3_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME1_PIPE3_RESET,
0);
+ break;
+ default:
+ break;
+ }
+ /* mec1 fw pc: CP_MEC1_INSTR_PNTR */
+ } else {
+ switch (ring->pipe) {
+ case 0:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE0_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE0_RESET,
0);
+ break;
+ case 1:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE1_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE1_RESET,
0);
+ break;
+ case 2:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE2_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE2_RESET,
0);
+ break;
+ case 3:
+ reset_pipe = REG_SET_FIELD(reset_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE3_RESET,
1);
+ clean_pipe = REG_SET_FIELD(clean_pipe,
CP_MEC_CNTL,
+ MEC_ME2_PIPE3_RESET,
0);
+ break;
+ default:
+ break;
+ }
+ /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */
+ }
+ WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);
+ WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);
+ r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)) -
mec_fw_start_pc;
+ }
+
+ soc21_grbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
+ gfx_v11_0_unset_safe_mode(adev, 0);
+
+ dev_info(adev->dev,"The ring %s pipe resets to MEC FW start PC: %s\n",
ring->name,
+ r == 0 ? "successfully" : "failed");
+ /*FIXME:Sometimes driver can't cache the MEC firmware start PC
correctly, so the pipe
+ * reset status relies on the compute ring test result.
+ */
+ return 0;
+}
+
static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
{
struct amdgpu_device *adev = ring->adev;
@@ -6774,8 +6905,10 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring,
unsigned int vmid)
r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
if (r) {
- dev_err(adev->dev, "reset via MMIO failed %d\n", r);
- return r;
+ dev_warn(adev->dev,"fail(%d) to reset kcq and try pipe
reset\n", r);
+ r = gfx_v11_0_reset_compute_pipe(ring);
+ if (r)
+ return r;
}
r = amdgpu_bo_reserve(ring->mqd_obj, false);
--
2.34.1
