[PATCH v2 2/2] drm/amdgpu: add db size and offset range for VCN and VPE

[Saleemkhan Jamadar]

VCN and VPE have different offset range, update the doorbell
offset range repsectively.
Doorbell size for VCN and VPE is 32bit .

v1 : add gfx switch case and fix checkpatch warnings (Shashank)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jama...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 24 ++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index 769154223e2d..acda3f3bf3e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
@@ -221,7 +221,29 @@ amdgpu_userqueue_get_doorbell_index(struct 
amdgpu_userq_mgr *uq_mgr,
                goto unpin_bo;
        }
 
-       db_size = sizeof(u64);
+       switch (db_info->queue_type) {
+       case AMDGPU_HW_IP_GFX:
+       case AMDGPU_HW_IP_COMPUTE:
+       case AMDGPU_HW_IP_DMA:
+               db_size = sizeof(u64);
+       break;
+
+       case AMDGPU_HW_IP_VCN_ENC:
+               db_size = sizeof(u32);
+               db_info->doorbell_offset += AMDGPU_NAVI10_DOORBELL64_VCN0_1 << 
1;
+       break;
+
+       case AMDGPU_HW_IP_VPE:
+               db_size = sizeof(u32);
+               db_info->doorbell_offset += AMDGPU_NAVI10_DOORBELL64_VPE << 1;
+       break;
+
+       default:
+               DRM_ERROR("[Usermode queues] IP %d not support\n", 
db_info->queue_type);
+               r = -EINVAL;
+               goto unpin_bo;
+       }
+
        index = amdgpu_doorbell_index_on_bar(uq_mgr->adev, db_obj->obj,
                                             db_info->doorbell_offset, db_size);
        DRM_DEBUG_DRIVER("[Usermode queues] doorbell index=%lld\n", index);
-- 
2.34.1