Use the helper for all non-SDMA code which queries the number
of SDMA instances.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 7 ++++---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 +++++++-----
10 files changed, 36 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index 946c48829f197..79d5a9e1e195b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -73,10 +73,12 @@ const char *hw_ip_names[MAX_HWIP] = {
static void amdgpu_devcoredump_fw_info(struct amdgpu_device *adev,
struct drm_printer *p)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
uint32_t version;
uint32_t feature;
uint8_t smu_program, smu_major, smu_minor, smu_debug;
struct atom_context *ctx = adev->mode_info.atom_context;
+ int i;
drm_printf(p, "VCE feature version: %u, fw version: 0x%08x\n",
adev->vce.fb_version, adev->vce.fw_version);
@@ -156,7 +158,7 @@ static void amdgpu_devcoredump_fw_info(struct amdgpu_device
*adev,
0, smu_program, version, smu_major, smu_minor, smu_debug);
/* SDMA firmware */
- for (int i = 0; i < adev->sdma.num_instances; i++) {
+ for (i = 0; i < num_sdma_inst; i++) {
drm_printf(p,
"SDMA%d feature version: %u, firmware version:
0x%08x\n",
i, adev->sdma.instance[i].feature_version,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 330f5cfb79218..4fee9ea68eefb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -213,6 +213,8 @@ static int amdgpu_firmware_info(struct
drm_amdgpu_info_firmware *fw_info,
struct drm_amdgpu_query_fw *query_fw,
struct amdgpu_device *adev)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
+
switch (query_fw->fw_type) {
case AMDGPU_INFO_FW_VCE:
fw_info->ver = adev->vce.fw_version;
@@ -318,7 +320,7 @@ static int amdgpu_firmware_info(struct
drm_amdgpu_info_firmware *fw_info,
}
break;
case AMDGPU_INFO_FW_SDMA:
- if (query_fw->index >= adev->sdma.num_instances)
+ if (query_fw->index >= num_sdma_inst)
return -EINVAL;
fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
fw_info->feature =
adev->sdma.instance[query_fw->index].feature_version;
@@ -424,7 +426,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
break;
case AMDGPU_HW_IP_DMA:
type = AMD_IP_BLOCK_TYPE_SDMA;
- for (i = 0; i < adev->sdma.num_instances; i++)
+ num_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
+ for (i = 0; i < num_inst; i++)
if (adev->sdma.instance[i].ring.sched.ready)
++num_rings;
ib_start_alignment = 256;
@@ -686,7 +689,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
count = 1;
break;
case AMD_IP_BLOCK_TYPE_SDMA:
- count = adev->sdma.num_instances;
+ count = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
break;
case AMD_IP_BLOCK_TYPE_JPEG:
count = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_JPEG) *
@@ -1649,6 +1652,7 @@ void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
{
struct amdgpu_device *adev = m->private;
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
struct drm_amdgpu_info_firmware fw_info;
struct drm_amdgpu_query_fw query_fw;
struct atom_context *ctx = adev->mode_info.atom_context;
@@ -1832,7 +1836,7 @@ static int amdgpu_debugfs_firmware_info_show(struct
seq_file *m, void *unused)
/* SDMA */
query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
- for (i = 0; i < adev->sdma.num_instances; i++) {
+ for (i = 0; i < num_sdma_inst; i++) {
query_fw.index = i;
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index bb946fa1e912e..462c6b27c8eba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -126,6 +126,7 @@ static void amdgpu_mes_doorbell_free(struct amdgpu_device
*adev)
int amdgpu_mes_init(struct amdgpu_device *adev)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
int i, r;
adev->mes.adev = adev;
@@ -156,7 +157,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
IP_VERSION(6, 0, 0))
adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
/* zero sdma_hqd_mask for non-existent engine */
- else if (adev->sdma.num_instances == 1)
+ else if (num_sdma_inst == 1)
adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
else
adev->mes.sdma_hqd_mask[i] = 0xfc;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 571f1c783bc66..1849f6a22e5f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -375,7 +375,8 @@ static void amdgpu_ras_instance_mask_check(struct
amdgpu_device *adev,
mask = GENMASK(num_xcc - 1, 0);
break;
case AMDGPU_RAS_BLOCK__SDMA:
- mask = GENMASK(adev->sdma.num_instances - 1, 0);
+ inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
+ mask = GENMASK(inst - 1, 0);
break;
case AMDGPU_RAS_BLOCK__VCN:
inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_VCN);
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 6d020e81ff945..c3183674ab552 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -37,6 +37,7 @@
void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
int i;
adev->doorbell_index.kiq = AMDGPU_DOORBELL_LAYOUT1_KIQ_START;
@@ -48,7 +49,7 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device
*adev)
adev->doorbell_index.xcc_doorbell_range =
AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE;
adev->doorbell_index.sdma_doorbell_range = 20;
- for (i = 0; i < adev->sdma.num_instances; i++)
+ for (i = 0; i < num_sdma_inst; i++)
adev->doorbell_index.sdma_engine[i] =
AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START +
i * (adev->doorbell_index.sdma_doorbell_range >> 1);
@@ -399,7 +400,7 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct
amdgpu_xcp_mgr *xcp_mgr, int x
int num_sdma, num_vcn, num_shared_vcn, num_xcp;
int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp;
- num_sdma = adev->sdma.num_instances;
+ num_sdma = amdgpu_device_ip_get_num_inst(adev, AMD_IP_BLOCK_TYPE_SDMA);
num_vcn = amdgpu_device_ip_get_num_inst(adev, AMD_IP_BLOCK_TYPE_VCN);
num_shared_vcn = 1;
@@ -463,7 +464,7 @@ static int aqua_vanjaram_get_xcp_res_info(struct
amdgpu_xcp_mgr *xcp_mgr,
return -EINVAL;
max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask);
- max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances;
+ max_res[AMDGPU_XCP_RES_DMA] = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
max_res[AMDGPU_XCP_RES_DEC] = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_VCN);
max_res[AMDGPU_XCP_RES_JPEG] = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_JPEG);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c4e15418e187e..7ba758500c7b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5687,12 +5687,13 @@ static void
gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device
/* Temporarily put sdma part here */
static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct
amdgpu_device *adev)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
const __le32 *fw_data;
uint32_t fw_size;
const struct sdma_firmware_header_v1_0 *sdma_hdr;
int i;
- for (i = 0; i < adev->sdma.num_instances; i++) {
+ for (i = 0; i < num_sdma_inst; i++) {
sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
adev->sdma.instance[i].fw->data;
fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 67cd420315719..fd24d7037a5a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5255,6 +5255,7 @@ static void
gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device
*adev,
bool enable)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
uint32_t def, data;
if (!(adev->cg_flags &
@@ -5338,7 +5339,7 @@ static void
gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
/* Some ASICs only have one SDMA instance, not need to
configure SDMA1 */
- if (adev->sdma.num_instances > 1) {
+ if (num_sdma_inst > 1) {
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL,
CGCG_INT_ENABLE, 1);
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
@@ -5372,7 +5373,7 @@ static void
gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
/* Some ASICs only have one SDMA instance, not need to
configure SDMA1 */
- if (adev->sdma.num_instances > 1) {
+ if (num_sdma_inst > 1) {
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index d0697b0869e3d..add31ae766d60 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3934,6 +3934,7 @@ static int gfx_v12_0_set_powergating_state(struct
amdgpu_ip_block *ip_block,
static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device
*adev,
bool enable)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
uint32_t def, data;
if (!(adev->cg_flags &
@@ -4017,7 +4018,7 @@ static void
gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
/* Some ASICs only have one SDMA instance, not need to
configure SDMA1 */
- if (adev->sdma.num_instances > 1) {
+ if (num_sdma_inst > 1) {
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL,
CGCG_INT_ENABLE, 1);
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
@@ -4051,7 +4052,7 @@ static void
gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
/* Some ASICs only have one SDMA instance, not need to
configure SDMA1 */
- if (adev->sdma.num_instances > 1) {
+ if (num_sdma_inst > 1) {
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index a59b4c36cad73..3b9f069801de2 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1272,11 +1272,12 @@ static int soc15_common_sw_fini(struct amdgpu_ip_block
*ip_block)
static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
{
+ int num_sdma_inst = amdgpu_device_ip_get_num_inst(adev,
AMD_IP_BLOCK_TYPE_SDMA);
int i;
/* sdma doorbell range is programed by hypervisor */
if (!amdgpu_sriov_vf(adev)) {
- for (i = 0; i < adev->sdma.num_instances; i++) {
+ for (i = 0; i < num_sdma_inst; i++) {
adev->nbio.funcs->sdma_doorbell_range(adev, i,
true, adev->doorbell_index.sdma_engine[i] << 1,
adev->doorbell_index.sdma_doorbell_range);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index ac0fdaa1ea23e..8e8af330db720 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -128,7 +128,7 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev
*kfd)
kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0;
BIT(2)=engine-0 queue-1; ... */
bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
- kfd->adev->sdma.num_instances *
+ amdgpu_device_ip_get_num_inst(kfd->adev,
AMD_IP_BLOCK_TYPE_SDMA) *
kfd->device_info.num_reserved_sdma_queues_per_engine);
break;
default:
@@ -1431,16 +1431,18 @@ unsigned int kfd_get_num_sdma_engines(struct kfd_node
*node)
{
/* If XGMI is not supported, all SDMA engines are PCIe */
if (!node->adev->gmc.xgmi.supported)
- return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
+ return amdgpu_device_ip_get_num_inst(node->adev,
AMD_IP_BLOCK_TYPE_SDMA) /
+ (int)node->kfd->num_nodes;
- return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
+ return min(amdgpu_device_ip_get_num_inst(node->adev,
AMD_IP_BLOCK_TYPE_SDMA) /
+ (int)node->kfd->num_nodes, 2);
}
unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
{
/* After reserved for PCIe, the rest of engines are XGMI */
- return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
- kfd_get_num_sdma_engines(node);
+ return amdgpu_device_ip_get_num_inst(node->adev,
AMD_IP_BLOCK_TYPE_SDMA) /
+ (int)node->kfd->num_nodes - kfd_get_num_sdma_engines(node);
}
int kgd2kfd_check_and_lock_kfd(void)
--
2.47.1
