From: Alex Deucher <alexander.deuc...@amd.com>
Now that all of the IP specific code has been moved into
the IP specific functions, we can make this code generic.
V2: Fixed build errors and porting logics (Shashank)
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Shashank Sharma <shashank.sha...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +--
...{mes_v11_0_userqueue.c => mes_userqueue.c} | 65 ++++++++++---------
...{mes_v11_0_userqueue.h => mes_userqueue.h} | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 +-
5 files changed, 45 insertions(+), 42 deletions(-)
rename drivers/gpu/drm/amd/amdgpu/{mes_v11_0_userqueue.c => mes_userqueue.c}
(85%)
rename drivers/gpu/drm/amd/amdgpu/{mes_v11_0_userqueue.h => mes_userqueue.h}
(91%)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c05183223cd5..21b926b16ad6 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -177,7 +177,7 @@ amdgpu-y += \
mes_v12_0.o \
# add GFX userqueue support
-amdgpu-$(CONFIG_DRM_AMDGPU_NAVI3X_USERQ) += mes_v11_0_userqueue.o
+amdgpu-$(CONFIG_DRM_AMDGPU_NAVI3X_USERQ) += mes_userqueue.o
# add UVD block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5b9005e39b92..0e5732795891 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -50,7 +50,7 @@
#include "gfx_v11_0_3.h"
#include "nbio_v4_3.h"
#include "mes_v11_0.h"
-#include "mes_v11_0_userqueue.h"
+#include "mes_userqueue.h"
#include "amdgpu_userq_fence.h"
#define GFX11_NUM_GFX_RINGS 1
@@ -1566,8 +1566,8 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block
*ip_block)
adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 4;
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
- adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;
- adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] =
&userq_mes_v11_0_funcs;
+ adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
+ adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
#endif
break;
case IP_VERSION(11, 0, 1):
@@ -1582,8 +1582,8 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block
*ip_block)
adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 4;
#ifdef CONFIG_DRM_AMD_USERQ_GFX
- adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;
- adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] =
&userq_mes_v11_0_funcs;
+ adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
+ adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
#endif
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
similarity index 85%
rename from drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
rename to drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index 45c57a8dfd90..fe50c85fb2ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
@@ -23,14 +23,15 @@
*/
#include "amdgpu.h"
#include "amdgpu_gfx.h"
-#include "mes_v11_0_userqueue.h"
+#include "mes_userqueue.h"
#include "amdgpu_userq_fence.h"
+#include "v11_structs.h"
#define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE
#define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE
static int
-mes_v11_0_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
+mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
{
int ret;
@@ -58,7 +59,7 @@ mes_v11_0_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
}
static int
-mes_v11_0_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
+mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
struct amdgpu_usermode_queue *queue,
uint64_t wptr)
{
@@ -86,7 +87,7 @@ mes_v11_0_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
return -EINVAL;
}
- ret = mes_v11_0_map_gtt_bo_to_gart(wptr_obj->obj);
+ ret = mes_userq_map_gtt_bo_to_gart(wptr_obj->obj);
if (ret) {
DRM_ERROR("Failed to map wptr bo to GART\n");
return ret;
@@ -96,9 +97,9 @@ mes_v11_0_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
return 0;
}
-static int mes_v11_0_userq_map(struct amdgpu_userq_mgr *uq_mgr,
- struct amdgpu_usermode_queue *queue,
- struct amdgpu_mqd_prop *userq_props)
+static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr,
+ struct amdgpu_usermode_queue *queue,
+ struct amdgpu_mqd_prop *userq_props)
{
struct amdgpu_device *adev = uq_mgr->adev;
struct amdgpu_userq_obj *ctx = &queue->fw_obj;
@@ -141,8 +142,8 @@ static int mes_v11_0_userq_map(struct amdgpu_userq_mgr
*uq_mgr,
return 0;
}
-static void mes_v11_0_userq_unmap(struct amdgpu_userq_mgr *uq_mgr,
- struct amdgpu_usermode_queue *queue)
+static void mes_userq_unmap(struct amdgpu_userq_mgr *uq_mgr,
+ struct amdgpu_usermode_queue *queue)
{
struct amdgpu_device *adev = uq_mgr->adev;
struct mes_remove_queue_input queue_input;
@@ -160,9 +161,9 @@ static void mes_v11_0_userq_unmap(struct amdgpu_userq_mgr
*uq_mgr,
DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r);
}
-static int mes_v11_0_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
- struct amdgpu_usermode_queue *queue,
- struct drm_amdgpu_userq_in
*mqd_user)
+static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
+ struct amdgpu_usermode_queue *queue,
+ struct drm_amdgpu_userq_in *mqd_user)
{
struct amdgpu_userq_obj *ctx = &queue->fw_obj;
int r, size;
@@ -182,7 +183,7 @@ static int mes_v11_0_userq_create_ctx_space(struct
amdgpu_userq_mgr *uq_mgr,
return 0;
}
-static void mes_v11_0_userq_set_fence_space(struct amdgpu_usermode_queue
*queue)
+static void mes_userq_set_fence_space(struct amdgpu_usermode_queue *queue)
{
struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr;
@@ -190,9 +191,9 @@ static void mes_v11_0_userq_set_fence_space(struct
amdgpu_usermode_queue *queue)
mqd->fenceaddress_hi = upper_32_bits(queue->fence_drv->gpu_addr);
}
-static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,
- struct drm_amdgpu_userq_in *args_in,
- struct amdgpu_usermode_queue *queue)
+static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,
+ struct drm_amdgpu_userq_in *args_in,
+ struct amdgpu_usermode_queue *queue)
{
struct amdgpu_device *adev = uq_mgr->adev;
struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type];
@@ -255,14 +256,15 @@ static int mes_v11_0_userq_mqd_create(struct
amdgpu_userq_mgr *uq_mgr,
if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) ||
!mqd_user->mqd) {
DRM_ERROR("Invalid GFX MQD\n");
- return -EINVAL;
+ r = -EINVAL;
+ goto free_mqd;
}
mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd),
mqd_user->mqd_size);
if (IS_ERR(mqd_gfx_v11)) {
DRM_ERROR("Failed to read user MQD\n");
- amdgpu_userqueue_destroy_object(uq_mgr, ctx);
- return -ENOMEM;
+ r = -ENOMEM;
+ goto free_mqd;
}
userq_props->shadow_addr = mqd_gfx_v11->shadow_va;
@@ -273,14 +275,15 @@ static int mes_v11_0_userq_mqd_create(struct
amdgpu_userq_mgr *uq_mgr,
if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) ||
!mqd_user->mqd) {
DRM_ERROR("Invalid SDMA MQD\n");
- return -EINVAL;
+ r = -EINVAL;
+ goto free_mqd;
}
mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd),
mqd_user->mqd_size);
if (IS_ERR(mqd_sdma_v11)) {
DRM_ERROR("Failed to read sdma user MQD\n");
- amdgpu_userqueue_destroy_object(uq_mgr, ctx);
- return -ENOMEM;
+ r = -ENOMEM;
+ goto free_mqd;
}
userq_props->csa_addr = mqd_sdma_v11->csa_va;
@@ -296,23 +299,23 @@ static int mes_v11_0_userq_mqd_create(struct
amdgpu_userq_mgr *uq_mgr,
}
/* Create BO for FW operations */
- r = mes_v11_0_userq_create_ctx_space(uq_mgr, queue, mqd_user);
+ r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user);
if (r) {
DRM_ERROR("Failed to allocate BO for userqueue (%d)", r);
goto free_mqd;
}
- mes_v11_0_userq_set_fence_space(queue);
+ mes_userq_set_fence_space(queue);
/* FW expects WPTR BOs to be mapped into GART */
- r = mes_v11_0_create_wptr_mapping(uq_mgr, queue,
userq_props->wptr_gpu_addr);
+ r = mes_userq_create_wptr_mapping(uq_mgr, queue,
userq_props->wptr_gpu_addr);
if (r) {
DRM_ERROR("Failed to create WPTR mapping\n");
goto free_ctx;
}
/* Map userqueue into FW using MES */
- r = mes_v11_0_userq_map(uq_mgr, queue, userq_props);
+ r = mes_userq_map(uq_mgr, queue, userq_props);
if (r) {
DRM_ERROR("Failed to init MQD\n");
goto free_ctx;
@@ -333,17 +336,17 @@ static int mes_v11_0_userq_mqd_create(struct
amdgpu_userq_mgr *uq_mgr,
}
static void
-mes_v11_0_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr,
+mes_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr,
struct amdgpu_usermode_queue *queue)
{
- mes_v11_0_userq_unmap(uq_mgr, queue);
+ mes_userq_unmap(uq_mgr, queue);
amdgpu_bo_unref(&queue->wptr_obj.obj);
amdgpu_userqueue_destroy_object(uq_mgr, &queue->fw_obj);
kfree(queue->userq_prop);
amdgpu_userqueue_destroy_object(uq_mgr, &queue->mqd);
}
-const struct amdgpu_userq_funcs userq_mes_v11_0_funcs = {
- .mqd_create = mes_v11_0_userq_mqd_create,
- .mqd_destroy = mes_v11_0_userq_mqd_destroy,
+const struct amdgpu_userq_funcs userq_mes_funcs =
+ .mqd_create = mes_userq_mqd_create,
+ .mqd_destroy = mes_userq_mqd_destroy,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h
b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.h
similarity index 91%
rename from drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h
rename to drivers/gpu/drm/amd/amdgpu/mes_userqueue.h
index 2c102361ca82..d0a521312ad4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h
+++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.h
@@ -22,9 +22,9 @@
*
*/
-#ifndef MES_V11_0_USERQ_H
-#define MES_V11_0_USERQ_H
+#ifndef MES_USERQ_H
+#define MES_USERQ_H
#include "amdgpu_userqueue.h"
-extern const struct amdgpu_userq_funcs userq_mes_v11_0_funcs;
+extern const struct amdgpu_userq_funcs userq_mes_funcs;
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 9af6aeeca063..4406e8ab4ff4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -43,7 +43,7 @@
#include "sdma_common.h"
#include "sdma_v6_0.h"
#include "v11_structs.h"
-#include "mes_v11_0_userqueue.h"
+#include "mes_userqueue.h"
MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
@@ -1380,7 +1380,7 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block
*ip_block)
DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
- adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_v11_0_funcs;
+ adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
#endif
r = amdgpu_sdma_sysfs_reset_mask_init(adev);
if (r)
--
2.46.2
