sysfs: cannot create duplicate filename
'/devices/pci0000:00/0000:00:01.1/0000:01:00.0/0000:02:00.0/0000:03:00.0/vcn_reset_mask'
[ 562.443738] CPU: 13 PID: 4888 Comm: modprobe Tainted: G E
6.10.0+ #51
[ 562.443740] Hardware name: AMD Splinter/Splinter-RPL, BIOS VS2683299N.FD
05/10/2023
[ 562.443741] Call Trace:
[ 562.443743] <TASK>
[ 562.443746] dump_stack_lvl+0x70/0x90
[ 562.443751] dump_stack+0x14/0x20
[ 562.443753] sysfs_warn_dup+0x60/0x80
[ 562.443757] sysfs_add_file_mode_ns+0x126/0x130
[ 562.443760] sysfs_create_file_ns+0x68/0xa0
[ 562.443762] device_create_file+0x46/0x90
[ 562.443766] amdgpu_vcn_sysfs_reset_mask_init+0x1c/0x30 [amdgpu]
[ 562.443991] vcn_v4_0_3_sw_init+0x270/0x3e0 [amdgpu]
[ 562.444120] amdgpu_device_init+0x1a0e/0x35a0 [amdgpu]
[ 562.444227] ? srso_alias_return_thunk+0x5/0xfbef5
[ 562.444230] ? pci_read_config_word+0x2d/0x50
[ 562.444235] amdgpu_driver_load_kms+0x1e/0xc0 [amdgpu]
[ 562.444340] amdgpu_pci_probe+0x1c3/0x660 [amdgpu]
[ 562.444451] local_pci_probe+0x4c/0xb0
For multiple vcn instances, to avoid creating reset sysfs multiple times,
add the instance paramter in reset mask init.
V2: create one sysfs file per instance. E.g.,
vcn_reset_mask, vcn1_reset_mask, vcn2_reset_mask, etc. (Alex)
Signed-off-by: Jesse Zhang <jesse.zh...@amd.com>
Suggested-by:Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 92 +++++++++++++++++++++++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 14 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 +--
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 8 +--
5 files changed, 104 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 25f490ad3a85..e3eab01ea38d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1289,32 +1289,114 @@ static ssize_t amdgpu_get_vcn_reset_mask(struct device
*dev,
if (!adev)
return -ENODEV;
- return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset);
+ return amdgpu_show_reset_mask(buf, adev->vcn.inst[0].supported_reset);
+}
+
+static ssize_t amdgpu_get_vcn1_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+ return -ENODEV;
+
+ return amdgpu_show_reset_mask(buf, adev->vcn.inst[1].supported_reset);
+}
+
+static ssize_t amdgpu_get_vcn2_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+ return -ENODEV;
+
+ return amdgpu_show_reset_mask(buf, adev->vcn.inst[2].supported_reset);
+}
+
+static ssize_t amdgpu_get_vcn3_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+ return -ENODEV;
+
+ return amdgpu_show_reset_mask(buf, adev->vcn.inst[3].supported_reset);
}
static DEVICE_ATTR(vcn_reset_mask, 0444,
amdgpu_get_vcn_reset_mask, NULL);
-int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev)
+static DEVICE_ATTR(vcn1_reset_mask, 0444,
+ amdgpu_get_vcn1_reset_mask, NULL);
+
+static DEVICE_ATTR(vcn2_reset_mask, 0444,
+ amdgpu_get_vcn2_reset_mask, NULL);
+
+static DEVICE_ATTR(vcn3_reset_mask, 0444,
+ amdgpu_get_vcn3_reset_mask, NULL);
+
+int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev, int inst)
{
int r = 0;
- if (adev->vcn.num_vcn_inst) {
+ switch (inst) {
+ case 0:
r = device_create_file(adev->dev, &dev_attr_vcn_reset_mask);
if (r)
return r;
+ break;
+ case 1:
+ r = device_create_file(adev->dev, &dev_attr_vcn1_reset_mask);
+ if (r)
+ return r;
+ break;
+ case 2:
+ r = device_create_file(adev->dev, &dev_attr_vcn2_reset_mask);
+ if (r)
+ return r;
+ break;
+ case 3:
+ r = device_create_file(adev->dev, &dev_attr_vcn3_reset_mask);
+ if (r)
+ return r;
+ break;
+ default:
+ break;
}
return r;
}
-void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev)
+void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev, int inst)
{
int idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- if (adev->vcn.num_vcn_inst)
+ switch (inst) {
+ case 0:
device_remove_file(adev->dev, &dev_attr_vcn_reset_mask);
+ break;
+ case 1:
+ device_remove_file(adev->dev,
&dev_attr_vcn1_reset_mask);
+ break;
+ case 2:
+ device_remove_file(adev->dev,
&dev_attr_vcn2_reset_mask);
+ break;
+ case 3:
+ device_remove_file(adev->dev,
&dev_attr_vcn3_reset_mask);
+ break;
+ default:
+ break;
+ }
+
drm_dev_exit(idx);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 7ff4ae2a0432..e655bc32a3cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -304,6 +304,7 @@ struct amdgpu_vcn_inst {
uint32_t vcn_codec_disable_mask;
struct delayed_work idle_work;
uint8_t work_inst;
+ uint32_t supported_reset;
};
struct amdgpu_vcn_ras {
@@ -332,7 +333,6 @@ struct amdgpu_vcn {
uint16_t inst_mask;
uint8_t num_inst_per_aid;
bool using_unified_queue;
- uint32_t supported_reset;
};
struct amdgpu_fw_shared_rb_ptrs_struct {
@@ -519,7 +519,7 @@ int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
enum AMDGPU_UCODE_ID ucode_id);
int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev, int inst);
-int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev);
-void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev);
+int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev, int inst);
+void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev, int inst);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 59f83409d323..f79008f51089 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -224,8 +224,8 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block
*ip_block)
vcn_v4_0_fw_shared_init(adev, inst);
/* TODO: Add queue reset mask when FW fully supports it */
- adev->sdma.supported_reset =
- amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
+ adev->vcn.inst[inst].supported_reset =
+
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[inst].ring_enc[0]);
done:
if (amdgpu_sriov_vf(adev)) {
@@ -250,11 +250,9 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block
*ip_block)
ip_block->ip_dump = ptr;
}
- if (inst == 0) {
- r = amdgpu_vcn_sysfs_reset_mask_init(adev);
- if (r)
- return r;
- }
+ r = amdgpu_vcn_sysfs_reset_mask_init(adev, inst);
+ if (r)
+ return r;
return 0;
}
@@ -292,7 +290,7 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- amdgpu_vcn_sysfs_reset_mask_fini(adev);
+ amdgpu_vcn_sysfs_reset_mask_fini(adev, inst);
r = amdgpu_vcn_sw_fini(adev, inst);
kfree(ip_block->ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index e9b869f373c9..b862c9c7e98f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -185,8 +185,8 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block
*ip_block)
fw_shared->sq.is_enabled = true;
/* TODO: Add queue reset mask when FW fully supports it */
- adev->sdma.supported_reset =
- amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
+ adev->vcn.inst[inst].supported_reset =
+
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[inst].ring_enc[0]);
if (amdgpu_vcnfw_log)
amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
@@ -217,7 +217,7 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block
*ip_block)
ip_block->ip_dump = ptr;
}
- r = amdgpu_vcn_sysfs_reset_mask_init(adev);
+ r = amdgpu_vcn_sysfs_reset_mask_init(adev, inst);
if (r)
return r;
@@ -254,7 +254,7 @@ static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- amdgpu_vcn_sysfs_reset_mask_fini(adev);
+ amdgpu_vcn_sysfs_reset_mask_fini(adev, inst);
r = amdgpu_vcn_sw_fini(adev, inst);
kfree(ip_block->ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 96ec01cffea3..703aa5ee7e6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -168,8 +168,8 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block
*ip_block)
fw_shared->sq.is_enabled = 1;
/* TODO: Add queue reset mask when FW fully supports it */
- adev->sdma.supported_reset =
- amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
+ adev->vcn.inst[inst].supported_reset =
+
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[inst].ring_enc[0]);
if (amdgpu_vcnfw_log)
amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
@@ -186,7 +186,7 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block
*ip_block)
ip_block->ip_dump = ptr;
}
- r = amdgpu_vcn_sysfs_reset_mask_init(adev);
+ r = amdgpu_vcn_sysfs_reset_mask_init(adev, inst);
if (r)
return r;
@@ -223,7 +223,7 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- amdgpu_vcn_sysfs_reset_mask_fini(adev);
+ amdgpu_vcn_sysfs_reset_mask_fini(adev, inst);
r = amdgpu_vcn_sw_fini(adev, inst);
kfree(ip_block->ip_dump);
--
2.25.1
