[PATCH] drm/amdgpu: Normalize reg offsets on JPEG v4.0.3

[Lijo Lazar]

Only local register offsets should be used on JPEG v4.0.3 as they cannot
handle remote access to other AIDs. Since only local offsets are used,
the special write to MCM_ADDR register is no longer needed.

Signed-off-by: Lijo Lazar <lijo.la...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 32 +++++++-----------------
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 6ae5a784e187..a07dc55c28ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -734,32 +734,20 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr, u64 seq
                0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
        amdgpu_ring_write(ring, 0);
 
-       if (ring->adev->jpeg.inst[ring->me].aid_id) {
-               amdgpu_ring_write(ring, 
PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
-                       0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x4);
-       } else {
-               amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
-               amdgpu_ring_write(ring, 0);
-       }
+       amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+       amdgpu_ring_write(ring, 0);
 
        amdgpu_ring_write(ring, 
PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                0, 0, PACKETJ_TYPE0));
        amdgpu_ring_write(ring, 0x3fbc);
 
-       if (ring->adev->jpeg.inst[ring->me].aid_id) {
-               amdgpu_ring_write(ring, 
PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
-                       0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x0);
-       } else {
-               amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
-               amdgpu_ring_write(ring, 0);
-       }
-
        amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
                0, 0, PACKETJ_TYPE0));
        amdgpu_ring_write(ring, 0x1);
 
+       amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+       amdgpu_ring_write(ring, 0);
+
        amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
        amdgpu_ring_write(ring, 0);
 }
@@ -834,9 +822,8 @@ void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring 
*ring, uint32_t reg,
 {
        uint32_t reg_offset;
 
-       /* For VF, only local offsets should be used */
-       if (amdgpu_sriov_vf(ring->adev))
-               reg = NORMALIZE_JPEG_REG_OFFSET(reg);
+       /* Only local offsets should be used */
+       reg = NORMALIZE_JPEG_REG_OFFSET(reg);
 
        reg_offset = (reg << 2);
 
@@ -881,9 +868,8 @@ void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring 
*ring, uint32_t reg, uint
 {
        uint32_t reg_offset;
 
-       /* For VF, only local offsets should be used */
-       if (amdgpu_sriov_vf(ring->adev))
-               reg = NORMALIZE_JPEG_REG_OFFSET(reg);
+       /* Only local offsets should be used */
+       reg = NORMALIZE_JPEG_REG_OFFSET(reg);
 
        reg_offset = (reg << 2);
 
-- 
2.25.1