On 2024-08-15 21:37, Hamza Mahfooz wrote:
> Hook up drm_crtc_vblank_on_config() in amdgpu_dm. So, that we can enable
> PSR and other static screen optimizations more quickly, while avoiding
> stuttering issues that are accompanied by the following dmesg error:
> 
> [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: 
> status=3
> 
> This also allows us to mimic how vblanking is handled by the windows
> amdgpu driver.
> 
> Signed-off-by: Hamza Mahfooz <hamza.mahf...@amd.com>
> ---
> v3: use a less conservative policy
> 
> [...]
>  
> @@ -8244,9 +8244,36 @@ static void manage_dm_interrupts(struct amdgpu_device 
> *adev,
>               amdgpu_display_crtc_idx_to_irq_type(
>                       adev,
>                       acrtc->crtc_id);
> +     struct drm_vblank_crtc_config config = {0};
> +     struct dc_crtc_timing *timing;
> +     int vsync_rate_hz;
> +     int offdelay = 30;
> +
> +     if (acrtc_state) {
> +             timing = &acrtc_state->stream->timing;
> +
> +             vsync_rate_hz = div64_u64(div64_u64((timing->pix_clk_100hz *
> +                                                  (u64)100),
> +                                                 timing->v_total),
> +                                       timing->h_total);

AFAICT this can be done with a single division:

                vsync_rate_hz = div64_u64((u64)timing->pix_clk_100hz * 100,
                                          (u64)timing->v_total * 
timing->h_total);


> +             if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
> +                 IP_VERSION(3, 5, 0) ||
> +                 acrtc_state->stream->link->psr_settings.psr_version <
> +                 DC_PSR_VERSION_UNSUPPORTED) {
> +                     if (vsync_rate_hz)
> +                             /* at least 2 frames */
> +                             offdelay = 2000 / vsync_rate_hz + 1;

Or even this:

  2000 / (timing->pix_clk_100hz * 100 / (timing->v_total * timing->h_total)) =

  2000 / 100 * timing->v_total * timing->h_total / timing->pix_clk_100hz =

  20 * timing->v_total * timing->h_total / timing->pix_clk_100hz

⇒ offdelay = div64_u64((u64)20 * timing->v_total * timing->h_total,
                       timing->pix_clk_100hz) + 1;


-- 
Earthling Michel Dänzer       \        GNOME / Xwayland / Mesa developer
https://redhat.com             \               Libre software enthusiast

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