[PATCH 18/22] drm/amd/display: Address coverity change

[Wayne Lin]

From: Chris Park <chris.p...@amd.com>

[Why]
Coverity picks up a defect with regards to array underflow.

[How]
Address coverity issue as recommended.

Reviewed-by: Leo Ma <hanghong...@amd.com>
Signed-off-by: Chris Park <chris.p...@amd.com>
Signed-off-by: Wayne Lin <wayne....@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c  | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index cce425dd62d2..01ea3a31e54d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -517,10 +517,12 @@ static void dcn401_update_clocks_update_dtb_dto(struct 
clk_mgr_internal *clk_mgr
                if (!use_hpo_encoder)
                        continue;
 
-               otg_master->clock_source->funcs->program_pix_clk(
+               if (otg_master->stream_res.pix_clk_params.controller_id > 
CONTROLLER_ID_UNDEFINED)
+                       otg_master->clock_source->funcs->program_pix_clk(
                                otg_master->clock_source,
                                &otg_master->stream_res.pix_clk_params,
-                               
dccg->ctx->dc->link_srv->dp_get_encoding_format(&otg_master->link_config.dp_link_settings),
+                               dccg->ctx->dc->link_srv->dp_get_encoding_format(
+                                       
&otg_master->link_config.dp_link_settings),
                                &otg_master->pll_settings);
        }
 }
-- 
2.37.3