[PATCH] drm/amdgpu: fix unbalanced parentheses in a #if0 region

[Masatake YAMATO]

Signed-off-by: Masatake YAMATO <yam...@redhat.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 06d787385ad4..27188dadfbcf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -741,12 +741,12 @@ static bool vce_v4_0_check_soft_reset(void *handle)
         */
        mutex_lock(&adev->grbm_idx_mutex);
        WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
-       if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & 
AMDGPU_VCE_STATUS_BUSY_MASK) {
+       if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & 
AMDGPU_VCE_STATUS_BUSY_MASK)) {
                srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 
SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
                srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 
SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
        }
        WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
-       if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & 
AMDGPU_VCE_STATUS_BUSY_MASK) {
+       if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & 
AMDGPU_VCE_STATUS_BUSY_MASK)) {
                srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 
SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
                srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 
SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
        }
@@ -936,16 +936,16 @@ static int vce_v4_0_set_clockgating_state(void *handle,
 
                if (enable) {
                        /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
-                       uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_CLOCK_GATING_A);
+                       uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_CLOCK_GATING_A));
                        data &= ~(0xf | 0xff0);
                        data |= ((0x0 << 0) | (0x04 << 4));
-                       WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, 
data);
+                       WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 
data);
 
                        /* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay 
*/
-                       data = RREG32(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_UENC_CLOCK_GATING);
+                       data = RREG32(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_UENC_CLOCK_GATING));
                        data &= ~(0xf | 0xff0);
                        data |= ((0x0 << 0) | (0x04 << 4));
-                       WREG32(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_UENC_CLOCK_GATING, data);
+                       WREG32(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_UENC_CLOCK_GATING), data);
                }
 
                vce_v4_0_set_vce_sw_clock_gating(adev, enable);
-- 
2.45.2