[AMD Official Use Only - General]
Ok, I miss this patch #2.
And please merge swsmu parts in patch#1 to patch#2. (patch #1 : powerplay,
patch #2: swsmu)
Reviewed-by: Yang Wang <kevinyang.w...@amd.com>
Best Regards,
Kevin
-----Original Message-----
From: Ma, Jun <jun....@amd.com>
Sent: Friday, May 10, 2024 9:00 AM
To: Wang, Yang(Kevin) <kevinyang.w...@amd.com>; Ma, Jun <jun....@amd.com>;
amd-gfx@lists.freedesktop.org
Cc: Ma, Jun <jun....@amd.com>; Feng, Kenneth <kenneth.f...@amd.com>; Deucher,
Alexander <alexander.deuc...@amd.com>; Koenig, Christian
<christian.koe...@amd.com>
Subject: Re: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile
setting on smu13 and smu14
On 5/9/2024 9:01 PM, Wang, Yang(Kevin) wrote:
> [AMD Official Use Only - General]
>
> please fix similar issues in other xxx_ppt.c file together? e. g:
> navi10_ppt.c, etc
>
Fix codes for navi10,vega20, etc. are in the patch 2 of this serial.
Regards,
Ma Jun
> Best Regards,
> Kevin
> -----Original Message-----
> From: Ma, Jun <jun....@amd.com>
> Sent: Thursday, May 9, 2024 5:37 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth <kenneth.f...@amd.com>; Deucher, Alexander
> <alexander.deuc...@amd.com>; Wang, Yang(Kevin)
> <kevinyang.w...@amd.com>; Koenig, Christian
> <christian.koe...@amd.com>; Ma, Jun <jun....@amd.com>
> Subject: [PATCH 1/2] drm/amdgpu/pm: Check input value for power
> profile setting on smu13 and smu14
>
> Check the input value for CUSTOM profile mode setting on smu13 and smu14.
> Otherwise it may cause out-of-bouds read error.
>
> Signed-off-by: Ma Jun <jun....@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++++
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 ++++
> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 5 +++++
> 3 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index e8b01662e164..6c24e2306383 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -2495,6 +2495,9 @@ static int smu_v13_0_0_set_power_profile_mode(struct
> smu_context *smu,
> }
>
> if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> + if (size != 9)
> + return -EINVAL;
> +
> ret = smu_cmn_update_table(smu,
> SMU_TABLE_ACTIVITY_MONITOR_COEFF,
> WORKLOAD_PPLIB_CUSTOM_BIT,
> @@ -2526,6 +2529,8 @@ static int smu_v13_0_0_set_power_profile_mode(struct
> smu_context *smu,
> activity_monitor->Fclk_PD_Data_error_coeff = input[7];
> activity_monitor->Fclk_PD_Data_error_rate_coeff =
> input[8];
> break;
> + default:
> + return -EINVAL;
> }
>
> ret = smu_cmn_update_table(smu, diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index e996a0a4d33e..4f98869e0284 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -2450,6 +2450,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct
> smu_context *smu, long *inp
> }
>
> if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> + if (size != 8)
> + return -EINVAL;
>
> ret = smu_cmn_update_table(smu,
> SMU_TABLE_ACTIVITY_MONITOR_COEFF,
> WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2478,6 +2480,8 @@ static int
> smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp
> activity_monitor->Fclk_MinActiveFreq = input[6];
> activity_monitor->Fclk_BoosterFreq = input[7];
> break;
> + default:
> + return -EINVAL;
> }
>
> ret = smu_cmn_update_table(smu, diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
> index 0d5ad531c764..3f040a4d374e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
> @@ -1418,6 +1418,9 @@ static int smu_v14_0_2_set_power_profile_mode(struct
> smu_context *smu,
> }
>
> if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> + if (size != 9)
> + return -EINVAL;
> +
> ret = smu_cmn_update_table(smu,
> SMU_TABLE_ACTIVITY_MONITOR_COEFF,
> WORKLOAD_PPLIB_CUSTOM_BIT,
> @@ -1449,6 +1452,8 @@ static int smu_v14_0_2_set_power_profile_mode(struct
> smu_context *smu,
> activity_monitor->Fclk_PD_Data_error_coeff = input[7];
> activity_monitor->Fclk_PD_Data_error_rate_coeff =
> input[8];
> break;
> + default:
> + return -EINVAL;
> }
>
> ret = smu_cmn_update_table(smu,
> --
> 2.34.1
>
