[PATCH v2 4/4] drm/amd/pm: Categorize RAS messages on SMUv13.0.6

[Lijo Lazar]

Set RAS priority handling capability for SMUv13.0.6 SOCs and categorize
RAS priority messages allowed.

Signed-off-by: Lijo Lazar <lijo.la...@amd.com>
---
v2: Move setting FW capability flags to IP specific code (Kevin)

 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 443233563a52..6e06729fb2e3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -144,7 +144,7 @@ static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COU
        MSG_MAP(GetDpmFreqByIndex,                   
PPSMC_MSG_GetDpmFreqByIndex,               1),
        MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,     
                0),
        MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,     
                1),
-       MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,  
                0),
+       MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,  
                SMU_MSG_RAS_PRI),
        MSG_MAP(DramLogSetDramAddrHigh,              
PPSMC_MSG_DramLogSetDramAddrHigh,          0),
        MSG_MAP(DramLogSetDramAddrLow,               
PPSMC_MSG_DramLogSetDramAddrLow,           0),
        MSG_MAP(DramLogSetDramSize,                  
PPSMC_MSG_DramLogSetDramSize,              0),
@@ -167,10 +167,10 @@ static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COU
        MSG_MAP(GetCTFLimit,                         PPSMC_MSG_GetCTFLimit,     
                0),
        MSG_MAP(GetThermalLimit,                     
PPSMC_MSG_ReadThrottlerLimit,              0),
        MSG_MAP(ClearMcaOnRead,                      PPSMC_MSG_ClearMcaOnRead,  
                0),
-       MSG_MAP(QueryValidMcaCount,                  
PPSMC_MSG_QueryValidMcaCount,              0),
-       MSG_MAP(QueryValidMcaCeCount,                
PPSMC_MSG_QueryValidMcaCeCount,            0),
-       MSG_MAP(McaBankDumpDW,                       PPSMC_MSG_McaBankDumpDW,   
                0),
-       MSG_MAP(McaBankCeDumpDW,                     PPSMC_MSG_McaBankCeDumpDW, 
                0),
+       MSG_MAP(QueryValidMcaCount,                  
PPSMC_MSG_QueryValidMcaCount,              SMU_MSG_RAS_PRI),
+       MSG_MAP(QueryValidMcaCeCount,                
PPSMC_MSG_QueryValidMcaCeCount,            SMU_MSG_RAS_PRI),
+       MSG_MAP(McaBankDumpDW,                       PPSMC_MSG_McaBankDumpDW,   
                SMU_MSG_RAS_PRI),
+       MSG_MAP(McaBankCeDumpDW,                     PPSMC_MSG_McaBankCeDumpDW, 
                SMU_MSG_RAS_PRI),
        MSG_MAP(SelectPLPDMode,                      PPSMC_MSG_SelectPLPDMode,  
                0),
        MSG_MAP(RmaDueToBadPageThreshold,            
PPSMC_MSG_RmaDueToBadPageThreshold,        0),
 };
@@ -3218,6 +3218,7 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
        smu->feature_map = smu_v13_0_6_feature_mask_map;
        smu->table_map = smu_v13_0_6_table_map;
        smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
+       smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
        smu_v13_0_set_smu_mailbox_registers(smu);
        amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
        amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
-- 
2.25.1