Hi Christian, [auto build test WARNING on pci/next] [also build test WARNING on next-20170710] [cannot apply to v4.12] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Christian-K-nig/PCI-add-a-define-for-the-PCI-resource-type-mask-v2/20170711-104904 base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next config: i386-allmodconfig (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): arch/x86/pci/fixup.c: In function 'pci_amd_enable_64bit_bar': >> arch/x86/pci/fixup.c:674:15: warning: large integer implicitly truncated to >> unsigned type [-Woverflow] res->start = 0x100000000ull; ^~~~~~~~~~~~~~ arch/x86/pci/fixup.c:675:13: warning: large integer implicitly truncated to unsigned type [-Woverflow] res->end = 0xfd00000000ull - 1; ^~~~~~~~~~~~~~~ >> arch/x86/pci/fixup.c:686:22: warning: right shift count >= width of type >> [-Wshift-count-overflow] high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | ^~ arch/x86/pci/fixup.c:687:21: warning: right shift count >= width of type [-Wshift-count-overflow] ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) ^~ vim +674 arch/x86/pci/fixup.c 634 635 /* 636 * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow 637 * configuring host bridge windows using the _PRS and _SRS methods. 638 * 639 * But this is rarely implemented, so we manually enable a large 64bit BAR for 640 * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here. 641 */ 642 static void pci_amd_enable_64bit_bar(struct pci_dev *dev) 643 { 644 struct resource *res, *conflict; 645 u32 base, limit, high; 646 unsigned i; 647 648 for (i = 0; i < 8; ++i) { 649 pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); 650 pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); 651 652 /* Is this slot free? */ 653 if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | 654 AMD_141b_MMIO_BASE_WE_MASK))) 655 break; 656 657 base >>= 8; 658 base |= high << 24; 659 660 /* Abort if a slot already configures a 64bit BAR. */ 661 if (base > 0x10000) 662 return; 663 } 664 if (i == 8) 665 return; 666 667 res = kzalloc(sizeof(*res), GFP_KERNEL); 668 if (!res) 669 return; 670 671 res->name = "PCI Bus 0000:00"; 672 res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | 673 IORESOURCE_MEM_64 | IORESOURCE_WINDOW; > 674 res->start = 0x100000000ull; 675 res->end = 0xfd00000000ull - 1; 676 677 /* Just grab the free area behind system memory for this */ 678 while ((conflict = request_resource_conflict(&iomem_resource, res))) 679 res->start = conflict->end + 1; 680 681 dev_info(&dev->dev, "adding root bus resource %pR\n", res); 682 683 base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | 684 AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; 685 limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; > 686 high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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