This patch is to update lsdma headers.
Signed-off-by: Yifan Zhang <yifan1.zh...@amd.com>
Reviewed-by: Tim Huang <tim.hu...@amd.com>
Reviewed-by: Lang Yu <lang...@amd.com>
---
.../drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_offset.h | 2 ++
.../drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_offset.h
index af560359e340..977997d27c32 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_offset.h
@@ -57,6 +57,8 @@
#define regLSDMA_HBM_PAGE_CONFIG_BASE_IDX
0
#define regLSDMA_UCODE_CHECKSUM
0x0029
#define regLSDMA_UCODE_CHECKSUM_BASE_IDX
0
+#define regLSDMA_F32_CNTL
0x002a
+#define regLSDMA_F32_CNTL_BASE_IDX
0
#define regLSDMA_FREEZE
0x002b
#define regLSDMA_FREEZE_BASE_IDX
0
#define regLSDMA_PF_PIO_STATUS
0x002c
diff --git a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h
index d1324239b751..d0d3a1c90ecc 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h
@@ -216,6 +216,11 @@
//LSDMA_UCODE_CHECKSUM
#define LSDMA_UCODE_CHECKSUM__DATA__SHIFT
0x0
#define LSDMA_UCODE_CHECKSUM__DATA_MASK
0xFFFFFFFFL
+//LSDMA_F32_CNTL
+#define LSDMA_F32_CNTL__HALT__SHIFT
0x0
+#define LSDMA_F32_CNTL__RESET__SHIFT
0x8
+#define LSDMA_F32_CNTL__HALT_MASK
0x00000001L
+#define LSDMA_F32_CNTL__RESET_MASK
0x00000100L
//LSDMA_FREEZE
#define LSDMA_FREEZE__PREEMPT__SHIFT
0x0
#define LSDMA_FREEZE__FREEZE__SHIFT
0x4
@@ -1034,6 +1039,7 @@
#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT
0xc
#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT
0xd
#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT
0x10
+#define LSDMA_QUEUE0_RB_CNTL__RB_PRIV__SHIFT
0x17
#define LSDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT
0x18
#define LSDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK
0x00000001L
#define LSDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK
0x0000003EL
@@ -1041,6 +1047,7 @@
#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK
0x00001000L
#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK
0x00002000L
#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK
0x001F0000L
+#define LSDMA_QUEUE0_RB_CNTL__RB_PRIV_MASK
0x00800000L
#define LSDMA_QUEUE0_RB_CNTL__RB_VMID_MASK
0x0F000000L
//LSDMA_QUEUE0_RB_BASE
#define LSDMA_QUEUE0_RB_BASE__ADDR__SHIFT
0x0
--
2.37.3
