I've attached two patches for RFC at the moment, I haven't finished
the userspace for these yet, but just wanted to get some
ideas/feedback.
Dave.
On 9 March 2017 at 13:52, Dave Airlie <airl...@gmail.com> wrote:
> On 28 February 2017 at 11:46, zhoucm1 <david1.z...@amd.com> wrote:
>> Hi Dave,
>>
>> The attached is our semaphore implementation, amdgpu_cs.c is drm file, the
>> others are kernel file.
>> Any suggestion?
> Thanks,
>
> I've built a tree with all these in it, and started looking into the
> interface.
>
> I do wonder if we need the separate sem signal/wait interface, I think
> we should just add
> semaphore chunks to the CS interface.
>
> I'm just playing around with this now.
>
> Dave.
From 66852d3e1dc42421eb1cfd9640c043bba70931af Mon Sep 17 00:00:00 2001
From: Dave Airlie <airl...@redhat.com>
Date: Thu, 9 Mar 2017 03:45:52 +0000
Subject: [PATCH 1/2] amdgpu/cs: split out fence dependency checking
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 86 +++++++++++++++++++---------------
1 file changed, 48 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d2d0f60..d72b6e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -961,56 +961,66 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
return 0;
}
-static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- struct amdgpu_cs_parser *p)
+static int amdgpu_process_fence_dep(struct amdgpu_device *adev,
+ struct amdgpu_cs_parser *p,
+ struct amdgpu_cs_chunk *chunk)
{
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- int i, j, r;
-
- for (i = 0; i < p->nchunks; ++i) {
- struct drm_amdgpu_cs_chunk_dep *deps;
- struct amdgpu_cs_chunk *chunk;
- unsigned num_deps;
+ unsigned num_deps;
+ int i, r;
+ struct drm_amdgpu_cs_chunk_dep *deps;
- chunk = &p->chunks[i];
+ deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
+ num_deps = chunk->length_dw * 4 /
+ sizeof(struct drm_amdgpu_cs_chunk_dep);
- if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
- continue;
+ for (i = 0; i < num_deps; ++i) {
+ struct amdgpu_ring *ring;
+ struct amdgpu_ctx *ctx;
+ struct dma_fence *fence;
- deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
- num_deps = chunk->length_dw * 4 /
- sizeof(struct drm_amdgpu_cs_chunk_dep);
+ r = amdgpu_cs_get_ring(adev, deps[i].ip_type,
+ deps[i].ip_instance,
+ deps[i].ring, &ring);
+ if (r)
+ return r;
- for (j = 0; j < num_deps; ++j) {
- struct amdgpu_ring *ring;
- struct amdgpu_ctx *ctx;
- struct dma_fence *fence;
+ ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
+ if (ctx == NULL)
+ return -EINVAL;
- r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
- deps[j].ip_instance,
- deps[j].ring, &ring);
+ fence = amdgpu_ctx_get_fence(ctx, ring,
+ deps[i].handle);
+ if (IS_ERR(fence)) {
+ r = PTR_ERR(fence);
+ amdgpu_ctx_put(ctx);
+ return r;
+ } else if (fence) {
+ r = amdgpu_sync_fence(adev, &p->job->sync,
+ fence);
+ dma_fence_put(fence);
+ amdgpu_ctx_put(ctx);
if (r)
return r;
+ }
+ }
+ return 0;
+}
- ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
- if (ctx == NULL)
- return -EINVAL;
+static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
+ struct amdgpu_cs_parser *p)
+{
+ int i, r;
- fence = amdgpu_ctx_get_fence(ctx, ring,
- deps[j].handle);
- if (IS_ERR(fence)) {
- r = PTR_ERR(fence);
- amdgpu_ctx_put(ctx);
- return r;
+ for (i = 0; i < p->nchunks; ++i) {
+ struct amdgpu_cs_chunk *chunk;
- } else if (fence) {
- r = amdgpu_sync_fence(adev, &p->job->sync,
- fence);
- dma_fence_put(fence);
- amdgpu_ctx_put(ctx);
- if (r)
- return r;
- }
+ chunk = &p->chunks[i];
+
+ if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
+ r = amdgpu_process_fence_dep(adev, p, chunk);
+ if (r)
+ return r;
}
}
--
2.7.4
From a41814e96ccbfc7929be05d30f2061e668c5b4af Mon Sep 17 00:00:00 2001
From: Dave Airlie <airl...@redhat.com>
Date: Wed, 8 Mar 2017 03:42:45 +0000
Subject: [PATCH 2/2] [RFC] drm/amdgpu: add shared semaphores support.
This is based on code provided by AMD (Chunming Zhou).
I've changed the code so the semaphore waits/signals are
passed in cs chunks rather than via separate ioctls.
This code is finished, I just wanted to ship it out early
in case anyone spots a problem, I'll finish off the libdrm
and radv bits and send more later.
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 70 ++++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +
drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 360 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h | 49 +++++
include/uapi/drm/amdgpu_drm.h | 31 +++
8 files changed, 532 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 2814aad..404bcba 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -24,7 +24,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
- amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o
+ amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_sem.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c1b9135..8a0f42f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -53,6 +53,7 @@
#include "amdgpu_ucode.h"
#include "amdgpu_ttm.h"
#include "amdgpu_gds.h"
+#include "amdgpu_sem.h"
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
#include "amdgpu_vm.h"
@@ -702,6 +703,8 @@ struct amdgpu_fpriv {
struct mutex bo_list_lock;
struct idr bo_list_handles;
struct amdgpu_ctx_mgr ctx_mgr;
+ spinlock_t sem_handles_lock;
+ struct idr sem_handles;
};
/*
@@ -1814,5 +1817,15 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
uint64_t addr, struct amdgpu_bo **bo);
int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
+int amdgpu_sem_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp);
+
+int amdgpu_sem_lookup_and_signal(struct amdgpu_fpriv *fpriv,
+ uint32_t handle,
+ struct dma_fence *fence);
+int amdgpu_sem_lookup_and_sync(struct amdgpu_device *adev,
+ struct amdgpu_fpriv *fpriv,
+ struct amdgpu_sync *sync,
+ uint32_t handle);
#include "amdgpu_object.h"
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d72b6e8..b561c61 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -217,6 +217,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
break;
case AMDGPU_CHUNK_ID_DEPENDENCIES:
+ case AMDGPU_CHUNK_ID_SEM_WAIT:
+ case AMDGPU_CHUNK_ID_SEM_SIGNAL:
break;
default:
@@ -1007,6 +1009,28 @@ static int amdgpu_process_fence_dep(struct amdgpu_device *adev,
return 0;
}
+static int amdgpu_process_sem_wait_dep(struct amdgpu_device *adev,
+ struct amdgpu_cs_parser *p,
+ struct amdgpu_cs_chunk *chunk)
+{
+ struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
+ unsigned num_deps;
+ int i, r;
+ struct drm_amdgpu_cs_chunk_dep *deps;
+
+ deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
+ num_deps = chunk->length_dw * 4 /
+ sizeof(struct drm_amdgpu_cs_chunk_dep);
+
+ for (i = 0; i < num_deps; ++i) {
+ r = amdgpu_sem_lookup_and_sync(adev, fpriv, &p->job->sync,
+ deps[i].handle);
+ if (r)
+ return r;
+ }
+ return 0;
+}
+
static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
struct amdgpu_cs_parser *p)
{
@@ -1021,12 +1045,56 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
r = amdgpu_process_fence_dep(adev, p, chunk);
if (r)
return r;
+ } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SEM_WAIT) {
+ r = amdgpu_process_sem_wait_dep(adev, p, chunk);
+ if (r)
+ return r;
}
}
return 0;
}
+static int amdgpu_process_sem_signal_dep(struct amdgpu_cs_parser *p,
+ struct amdgpu_cs_chunk *chunk,
+ struct dma_fence *fence)
+{
+ struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
+ unsigned num_deps;
+ int i, r;
+ struct drm_amdgpu_cs_chunk_dep *deps;
+
+ deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
+ num_deps = chunk->length_dw * 4 /
+ sizeof(struct drm_amdgpu_cs_chunk_dep);
+
+ for (i = 0; i < num_deps; ++i) {
+ r = amdgpu_sem_lookup_and_signal(fpriv, deps[i].handle,
+ fence);
+ if (r)
+ return r;
+ }
+ return 0;
+}
+
+static int amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
+{
+ int i, r;
+
+ for (i = 0; i < p->nchunks; ++i) {
+ struct amdgpu_cs_chunk *chunk;
+
+ chunk = &p->chunks[i];
+
+ if (chunk->chunk_id == AMDGPU_CHUNK_ID_SEM_SIGNAL) {
+ r = amdgpu_process_sem_signal_dep(p, chunk, p->fence);
+ if (r)
+ return r;
+ }
+ }
+ return 0;
+}
+
static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
union drm_amdgpu_cs *cs)
{
@@ -1054,7 +1122,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
trace_amdgpu_cs_ioctl(job);
amd_sched_entity_push_job(&job->base);
- return 0;
+ return amdgpu_cs_post_dependencies(p);
}
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index cf05006..67a4157 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -86,6 +86,7 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
for (i = 0; i < adev->num_rings; i++)
amd_sched_entity_fini(&adev->rings[i]->sched,
&ctx->rings[i].entity);
+
}
static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 61d94c7..5b3e3b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -664,6 +664,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
mutex_init(&fpriv->bo_list_lock);
idr_init(&fpriv->bo_list_handles);
+ spin_lock_init(&fpriv->sem_handles_lock);
+ idr_init(&fpriv->sem_handles);
amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
file_priv->driver_priv = fpriv;
@@ -689,6 +691,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_bo_list *list;
+ struct amdgpu_sem *sem;
int handle;
if (!fpriv)
@@ -711,8 +714,12 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
amdgpu_bo_list_free(list);
+
+//TODO idr_for_each_entry(&fpriv->sem_handles, sem, handle)
+// amdgpu_sem_destroy(fpriv, handle);
idr_destroy(&fpriv->bo_list_handles);
+ idr_destroy(&fpriv->sem_handles);
mutex_destroy(&fpriv->bo_list_lock);
kfree(fpriv);
@@ -896,6 +903,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
};
const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
new file mode 100644
index 0000000..c7502f8
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
@@ -0,0 +1,360 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Chunming Zhou <david1.z...@amd.com>
+ */
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/poll.h>
+#include <linux/seq_file.h>
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/anon_inodes.h>
+#include "amdgpu_sem.h"
+#include "amdgpu.h"
+#include <drm/drmP.h>
+
+static void amdgpu_sem_core_free(struct kref *kref)
+{
+ struct amdgpu_sem_core *core = container_of(
+ kref, struct amdgpu_sem_core, kref);
+
+ if (core->file)
+ fput(core->file);
+
+ dma_fence_put(core->fence);
+ mutex_destroy(&core->lock);
+ kfree(core);
+}
+
+static void amdgpu_sem_free(struct kref *kref)
+{
+ struct amdgpu_sem *sem = container_of(
+ kref, struct amdgpu_sem, kref);
+
+ kref_put(&sem->base->kref, amdgpu_sem_core_free);
+ kfree(sem);
+}
+
+static inline void amdgpu_sem_get(struct amdgpu_sem *sem)
+{
+ if (sem)
+ kref_get(&sem->kref);
+}
+
+static inline void amdgpu_sem_put(struct amdgpu_sem *sem)
+{
+ if (sem)
+ kref_put(&sem->kref, amdgpu_sem_free);
+}
+
+static int amdgpu_sem_release(struct inode *inode, struct file *file)
+{
+ struct amdgpu_sem_core *core = file->private_data;
+
+ kref_put(&core->kref, amdgpu_sem_core_free);
+ return 0;
+}
+
+static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait)
+{
+ return 0;
+}
+
+static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg)
+{
+ return 0;
+}
+
+static const struct file_operations amdgpu_sem_fops = {
+ .release = amdgpu_sem_release,
+ .poll = amdgpu_sem_poll,
+ .unlocked_ioctl = amdgpu_sem_file_ioctl,
+ .compat_ioctl = amdgpu_sem_file_ioctl,
+};
+
+
+static inline struct amdgpu_sem *amdgpu_sem_lookup(struct amdgpu_fpriv *fpriv, u32 handle)
+{
+ struct amdgpu_sem *sem;
+
+ spin_lock(&fpriv->sem_handles_lock);
+
+ /* Check if we currently have a reference on the object */
+ sem = idr_find(&fpriv->sem_handles, handle);
+ amdgpu_sem_get(sem);
+
+ spin_unlock(&fpriv->sem_handles_lock);
+
+ return sem;
+}
+
+static struct amdgpu_sem_core *amdgpu_sem_core_alloc(void)
+{
+ struct amdgpu_sem_core *core;
+
+ core = kzalloc(sizeof(*core), GFP_KERNEL);
+ if (!core)
+ return NULL;
+
+ kref_init(&core->kref);
+ mutex_init(&core->lock);
+ return core;
+}
+
+static struct amdgpu_sem *amdgpu_sem_alloc(void)
+{
+ struct amdgpu_sem *sem;
+
+ sem = kzalloc(sizeof(*sem), GFP_KERNEL);
+ if (!sem)
+ return NULL;
+
+ kref_init(&sem->kref);
+
+ return sem;
+}
+
+static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle)
+{
+ struct amdgpu_sem *sem;
+ struct amdgpu_sem_core *core;
+ int ret;
+
+ sem = amdgpu_sem_alloc();
+ core = amdgpu_sem_core_alloc();
+ if (!sem || !core) {
+ kfree(sem);
+ kfree(core);
+ return -ENOMEM;
+ }
+
+ sem->base = core;
+
+ idr_preload(GFP_KERNEL);
+ spin_lock(&fpriv->sem_handles_lock);
+
+ ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT);
+
+ spin_unlock(&fpriv->sem_handles_lock);
+ idr_preload_end();
+
+ if (ret < 0)
+ return ret;
+
+ *handle = ret;
+ return 0;
+}
+
+static int amdgpu_sem_signal(struct amdgpu_fpriv *fpriv,
+ u32 handle, struct dma_fence *fence)
+{
+ struct amdgpu_sem *sem;
+ struct amdgpu_sem_core *core;
+
+ sem = amdgpu_sem_lookup(fpriv, handle);
+ if (!sem)
+ return -EINVAL;
+
+ core = sem->base;
+ mutex_lock(&core->lock);
+ dma_fence_put(core->fence);
+ core->fence = dma_fence_get(fence);
+ mutex_unlock(&core->lock);
+
+ amdgpu_sem_put(sem);
+ return 0;
+}
+
+static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv,
+ int fd, u32 *handle)
+{
+ struct file *file = fget(fd);
+ struct amdgpu_sem *sem;
+ struct amdgpu_sem_core *core;
+ int ret;
+
+ if (!file)
+ return -EINVAL;
+
+ core = file->private_data;
+ if (!core) {
+ fput(file);
+ return -EINVAL;
+ }
+
+ mutex_lock(&core->lock);
+ kref_get(&core->kref);
+ mutex_unlock(&core->lock);
+ sem = amdgpu_sem_alloc();
+ if (!sem) {
+ ret = -ENOMEM;
+ goto err_sem;
+ }
+
+ sem->base = core;
+
+ idr_preload(GFP_KERNEL);
+ spin_lock(&fpriv->sem_handles_lock);
+
+ ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT);
+
+ spin_unlock(&fpriv->sem_handles_lock);
+ idr_preload_end();
+
+ if (ret < 0)
+ goto err_out;
+
+ *handle = ret;
+ fput(file);
+ return 0;
+err_sem:
+ kref_put(&core->kref, amdgpu_sem_core_free);
+err_out:
+ amdgpu_sem_put(sem);
+ fput(file);
+ return ret;
+
+}
+
+static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv,
+ u32 handle, int *fd)
+{
+ struct amdgpu_sem *sem;
+ struct amdgpu_sem_core *core;
+ int ret;
+
+ sem = amdgpu_sem_lookup(fpriv, handle);
+ if (!sem)
+ return -EINVAL;
+
+ core = sem->base;
+ mutex_lock(&core->lock);
+ if (!core->file) {
+ core->file = anon_inode_getfile("sem_file",
+ &amdgpu_sem_fops,
+ core, 0);
+ if (IS_ERR(core->file)) {
+ mutex_unlock(&core->lock);
+ ret = -ENOMEM;
+ goto err_put_sem;
+ }
+ }
+ kref_get(&core->kref);
+ mutex_unlock(&core->lock);
+
+ ret = get_unused_fd_flags(O_CLOEXEC);
+ if (ret < 0)
+ goto err_put_file;
+
+ fd_install(ret, core->file);
+
+ *fd = ret;
+ amdgpu_sem_put(sem);
+ return 0;
+
+err_put_file:
+ kref_put(&core->kref, amdgpu_sem_core_free);
+ fput(core->file);
+err_put_sem:
+ amdgpu_sem_put(sem);
+ return ret;
+}
+
+void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle)
+{
+ struct amdgpu_sem *sem = amdgpu_sem_lookup(fpriv, handle);
+ if (!sem)
+ return;
+
+ spin_lock(&fpriv->sem_handles_lock);
+ idr_remove(&fpriv->sem_handles, handle);
+ spin_unlock(&fpriv->sem_handles_lock);
+ kref_put(&sem->kref, amdgpu_sem_free);
+
+ kref_put(&sem->kref, amdgpu_sem_free);
+}
+
+int amdgpu_sem_lookup_and_sync(struct amdgpu_device *adev,
+ struct amdgpu_fpriv *fpriv,
+ struct amdgpu_sync *sync,
+ uint32_t handle)
+{
+ int r;
+ struct amdgpu_sem *sem;
+
+ sem = amdgpu_sem_lookup(fpriv, handle);
+ if (!sem)
+ return -EINVAL;
+
+ r = amdgpu_sync_fence(adev, sync, sem->base->fence);
+ if (r)
+ goto err;
+ mutex_lock(&sem->base->lock);
+ dma_fence_put(sem->base->fence);
+ sem->base->fence = NULL;
+ mutex_unlock(&sem->base->lock);
+
+err:
+ amdgpu_sem_put(sem);
+ return r;
+
+}
+
+int amdgpu_sem_lookup_and_signal(struct amdgpu_fpriv *fpriv,
+ uint32_t handle,
+ struct dma_fence *fence)
+{
+ return amdgpu_sem_signal(fpriv, handle, fence);
+}
+
+int amdgpu_sem_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *filp)
+{
+ union drm_amdgpu_sem *args = data;
+ struct amdgpu_fpriv *fpriv = filp->driver_priv;
+ int r = 0;
+
+ switch (args->in.op) {
+ case AMDGPU_SEM_OP_CREATE_SEM:
+ r = amdgpu_sem_create(fpriv, &args->out.handle);
+ break;
+ case AMDGPU_SEM_OP_IMPORT_SEM:
+ r = amdgpu_sem_import(fpriv, args->in.handle, &args->out.handle);
+ break;
+ case AMDGPU_SEM_OP_EXPORT_SEM:
+ r = amdgpu_sem_export(fpriv, args->in.handle, &args->out.fd);
+ break;
+ case AMDGPU_SEM_OP_DESTROY_SEM:
+ amdgpu_sem_destroy(fpriv, args->in.handle);
+ break;
+ default:
+ r = -EINVAL;
+ break;
+ }
+
+ return r;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h
new file mode 100644
index 0000000..a4457c2
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Chunming Zhou <david1.z...@amd.com>
+ *
+ */
+
+
+#ifndef _LINUX_AMDGPU_SEM_H
+#define _LINUX_AMDGPU_SEM_H
+
+#include <linux/types.h>
+#include <linux/kref.h>
+#include <linux/ktime.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/dma-fence.h>
+
+struct amdgpu_sem_core {
+ struct file *file;
+ struct kref kref;
+ struct dma_fence *fence;
+ struct mutex lock;
+};
+
+struct amdgpu_sem {
+ struct amdgpu_sem_core *base;
+ struct kref kref;
+};
+
+#endif /* _LINUX_AMDGPU_SEM_H */
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 5797283..d3ecdaf 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -51,6 +51,7 @@ extern "C" {
#define DRM_AMDGPU_GEM_OP 0x10
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
+#define DRM_AMDGPU_SEM 0x13
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -65,6 +66,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
+#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -335,6 +337,33 @@ union drm_amdgpu_wait_fences {
struct drm_amdgpu_wait_fences_out out;
};
+#define AMDGPU_SEM_OP_CREATE_SEM 0
+//efine AMDGPU_SEM_OP_WAIT_SEM 1
+//efine AMDGPU_SEM_OP_SIGNAL_SEM 2
+#define AMDGPU_SEM_OP_IMPORT_SEM 3
+#define AMDGPU_SEM_OP_EXPORT_SEM 4
+#define AMDGPU_SEM_OP_DESTROY_SEM 5
+
+struct drm_amdgpu_sem_in {
+ __u32 ctx_id;
+ __u32 ip_type;
+ __u32 ip_instance;
+ __u32 ring;
+ __u32 op;
+ __u32 seq;
+ __u32 handle;
+};
+
+struct drm_amdgpu_sem_out {
+ __u32 fd;
+ __u32 handle;
+};
+
+union drm_amdgpu_sem {
+ struct drm_amdgpu_sem_in in;
+ struct drm_amdgpu_sem_out out;
+};
+
#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
#define AMDGPU_GEM_OP_SET_PLACEMENT 1
@@ -390,6 +419,8 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_IB 0x01
#define AMDGPU_CHUNK_ID_FENCE 0x02
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
+#define AMDGPU_CHUNK_ID_SEM_WAIT 0x04
+#define AMDGPU_CHUNK_ID_SEM_SIGNAL 0x05
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
--
2.7.4
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