> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Flora Cui
> Sent: Thursday, December 15, 2016 3:31 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Cui, Flora
> Subject: [PATCH 1/2] drm/amdgpu: update tile table for verde
>
> Change-Id: I4e3c698a04e5f7ee05c0268eec12df519f2305d4
> Signed-off-by: Flora Cui <flora....@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Marek or Nicolai,
Will this cause any issues with mesa? I think we should be ok on amdgpu.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 295
> +++++++++++++++++++++++++++++++++-
> 1 file changed, 293 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 22c3d36..ce75d46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -411,8 +411,299 @@ static void gfx_v6_0_tiling_mode_table_init(struct
> amdgpu_device *adev)
> break;
> }
>
> - if (adev->asic_type == CHIP_VERDE ||
> - adev->asic_type == CHIP_OLAND ||
> + if (adev->asic_type == CHIP_VERDE) {
> + for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++) {
> + switch (reg_offset) {
> + case 0:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 1:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 2:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 3:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_8_BANK) |
> +
> TILE_SPLIT(split_equal_to_row_size));
> + break;
> + case 4:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> + break;
> + case 5:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_4_BANK));
> + break;
> + case 6:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_4_BANK));
> + break;
> + case 7:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_2_BANK));
> + break;
> + case 8:
> + gb_tile_moden =
> (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
> + break;
> + case 9:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> + break;
> + case 10:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 11:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 12:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 13:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> + break;
> + case 14:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 15:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 16:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK));
> + break;
> + case 17:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> TILE_SPLIT(split_equal_to_row_size));
> + break;
> + case 18:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> + break;
> + case 19:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> TILE_SPLIT(split_equal_to_row_size));
> + break;
> + case 20:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> TILE_SPLIT(split_equal_to_row_size));
> + break;
> + case 21:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_8_BANK));
> + break;
> + case 22:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_8_BANK));
> + break;
> + case 23:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_4_BANK));
> + break;
> + case 24:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_4_BANK));
> + break;
> + case 25:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_2_BANK));
> + break;
> + case 26:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_2_BANK));
> + break;
> + case 27:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_2_BANK));
> + break;
> + case 28:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_2_BANK));
> + break;
> + case 29:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_2_BANK));
> + break;
> + case 30:
> + gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> +
> NUM_BANKS(ADDR_SURF_2_BANK));
> + break;
> + default:
> + continue;
> + }
> + adev->gfx.config.tile_mode_array[reg_offset] =
> gb_tile_moden;
> + WREG32(mmGB_TILE_MODE0 + reg_offset,
> gb_tile_moden);
> + }
> + } else if (adev->asic_type == CHIP_OLAND ||
> adev->asic_type == CHIP_HAINAN) {
> for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++) {
> switch (reg_offset) {
> --
> 2.7.4
>
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