Can you please elaborate your answer ... ? On Wed, Jan 30, 2013 at 10:37 PM, Don <[email protected]> wrote:
> You have to identify the bottleneck in the pipeline. The time required > for the bottleneck is the steady state time per operation of the > pipelined processing. Then determine the time to do the 4 stages > sequentially. The difference is the speed up. > > Don > > On Jan 30, 11:59 am, Ayush Kapoor <[email protected]> wrote: > > Consider an instruction pipeline with four stages (S1, S2, S3 and S4) > each > > with combinational circuit only. The pipeline registers are required > > between each stage and at the end of the last stage. Delays for the > stages > > and for the pipeline registers are as given in the figure. > > > > What is the approximate speed up of the pipeline in steady state under > > ideal conditions when compared to the corresponding non-pipeline > > implementation? [2 marks] > > (A) 4.0 > > (B) 2.5 > > (C) 1.1 > > (D) 3.0 > > > > Answer to this question is 2.5 > > Can anybody explain me how to solve this question? > > -- > You received this message because you are subscribed to the Google Groups > "Algorithm Geeks" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/groups/opt_out. > > > -- Ayush -- You received this message because you are subscribed to the Google Groups "Algorithm Geeks" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
