I have a couple of reasons to avoid changing the metric to include anything but n-NOR DCG complexity:
1) A lot of the resistance to adopting lossless compression as model selection criterion is based on Kolmogorov Complexity's open parameter: Choice of UTM. Indeed, I see the psychological appeal of this specious critique as perhaps the primary barrier to advancement the applied sciences. It is more of a barrier than arguments over choice of resource limits or conflation of "is" (AIT) with "ought" (SDT) in AIXI. Even Schmidhuber gets hung up on this when it comes to machine learning because he thinks choice of neural network architecture is analogous to an "instruction set" and thereby renders things too fuzzy. For crying out loud, Solomonoff himself, in his final days, went so far as to proclaim that choice of UTM as an open parameter was "good" because it permitted some sort of cultural relativism or something. ENOUGH!!! 2) A strictly n-NOR DCG contest may well receive funding from the likes of Federico Faggin -- for the same reason he underwrote The Boundary Institute. This is _particularly_ the case if some way of permitting DCG's as opposed to DAG's can be found. On Fri, Oct 15, 2021 at 4:44 PM Matt Mahoney <[email protected]> wrote: > > > On Fri, Oct 15, 2021, 4:50 PM <[email protected]> wrote: > >> So the goal is to make a circuit (?_that is ONLY made of NOR >> components_?) that outputs a 1 only when the input is enwik9? Hence the >> size of said circuit is the score? How do you know if some other input ex. >> enwik8 wouldn't pop out a 1? You'd have to feed in all possible inputs to >> see if does, no? >> > > In general, yes, unless P = NP. It's a minor variation of SAT. The best > known solution time increases exponentially with the size of the circuit > description. > > Thus, my proposal that is easier to test. (Input is 33 bit n, output is > n'th bit of enwik9). You don't even need to specify hardware constraints > because run time and memory only depend on the size of the circuit. > > It might be interesting to expand this beyond NOR gates to a more general > hardware description language that could be implemented more efficiently on > a computer. So you could have adders, multipliers, parallel vector logic > operators, etc, which in principle could all be made of NOR gates. We would > keep the requirement of a feed forward network only, with no clock, > registers, memory, or feedback loops. > >> *Artificial General Intelligence List <https://agi.topicbox.com/latest>* > / AGI / see discussions <https://agi.topicbox.com/groups/agi> + > participants <https://agi.topicbox.com/groups/agi/members> + > delivery options <https://agi.topicbox.com/groups/agi/subscription> > Permalink > <https://agi.topicbox.com/groups/agi/T728994814c1a40a0-M6f56ea716cf1180c5b8b3209> > ------------------------------------------ Artificial General Intelligence List: AGI Permalink: https://agi.topicbox.com/groups/agi/T728994814c1a40a0-M6c3654c88d7b99007795338a Delivery options: https://agi.topicbox.com/groups/agi/subscription
