My knowledge being limited in this area, I guess that when x86
announces, say, 8 cores / 16 threads, the two threads by core are
handled using superscalar (possibly pipelining): instead of executing
in parallel multiple instructions of one program, they allow to execute
in parallel multiple instructions of two distinct programs?
But there are differences between physical cores and logical ones
(hardware threads): the local APIC table is uniq to the physical core.
This does mean that the NIX approach will handle physical cores, and
that a kernel allocated to some physical core will be perhaps able to
use (in this case) two logical cores (hardware threads)?
--
Thierry Laronde <tlaronde +AT+ kergis +dot+ com>
http://www.kergis.com/
http://kertex.kergis.com/
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