> This looks like it fits the bill: open, small, simple. How was it formally > verified?
http://www.clifford.at/papers/2017/riscv-formal/slides.pdf > How can I help with the compiler port? Compiling & testing lots of library code would likely reveal remaining bugs. Also it might be useful to adapt the arm soft floating point code to use on RISC-V cores without hardware fp (like picorv32 or HiFive1). A 64-bit version of the compiler might also be of interest. Contact me off-list to join in. > Which fpga board do you recommend? I use the myStorm BlackIce https://www.tindie.com/products/Folknology/blackice-ii/ with a Lattice ICE40 FPGA. Not as powerful as altera or xilinx, but it works with yosys (Clifford's open-source verilog toolchain). For experimenting with a real RISC-V ASIC there's HiFive1 (has hardly any RAM so small embedded projects only). The HiFive Unleashed should be capable of running Plan 9 but will be expensive.