I'm trying to bring up Plan 9 on a new motherboard (intel DH61DL)
and getting a very odd problem. The immediate symptom is
panic: assert failed at 0xf01556f3: lapictimer.hz != 0
which is occurring because all reads to the local apic registers
are returning 0xFFFFFFFF.
I've verified that I can read the lapic from l.s before turning
the mmu on, getting sensible values from the registers.
By calling mmuwalk() I've verified that vmap() has put the right value
in the PTE to map the lapic area uncached:
vmap 0xfee00000 1024 => 0xe0000000
pte (pdb=f0012000) @f0019000 = fee00013
I've verified that the mtrr settings have the lapic regs uncached
(provided that nesting of entries works correctly, since there are
4GB of RAM installed):
cache default uc
cache 0x0 4294967296 wb
cache 0x100000000 536870912 wb
cache 0xdb800000 8388608 uc
cache 0xdc000000 67108864 uc
cache 0xe0000000 536870912 uc
cache 0x11f600000 2097152 uc
cache 0x11f800000 8388608 uc
I've thrown in a few wbinvd() and flushpg() calls out of general
paranoia. Nothing helps.
Can anyone suggest an avenue of investigation? Surely I'm not the
first to try running native Plan 9 with 4GB of RAM?
