On Thu, 08 Jan 2009 12:09:51 EST ge...@plan9.bell-labs.com wrote: > You don't want to use an amd29k (even if you could get one). > They look cute on paper but their freeze-mode interrupt > handling is a Chinese puzzle and unless you use Ken's compiler > (previously called 9c), you're stuck with register windows, > which tend to need to be spilled when an interrupt occurs, > thus slowing interrupt response unpredictably.
It was called freeze mode because on *any* trap/interrupts it disabled interrupts (and IIRC most traps). Its designers tried to apply the "RISC philosophy" to interrupt handling as well and left most everything upto software. Its freeze mode trap/interrupt handling was actually pretty simple as the processor did very little for you! If you could do everything in the handler, you didn't need to save any registers (except the ones you need in the handler). So for instance TLB handling was a few instructions, done entirely in freeze mode (unless the page table was invalid). Trap code to vector to a user mode register spill/fill code handler was about 5 instructions. The user mode spill/fill handlers were about 10 instructions each and they were interruptible. The painful part was preparing things to call a C language interrupt handler as it required a consistent stack but interrupt can occur in the middle of a spill/fill. You can save all 128 registers (+ a few special registers) but typically the code tried to save only the registers in use; and this added a lot of complexity and variable latency. It would've been better off with a pair of instructions to load/store full context (just like in all the CISCs!). But of course with so many registers the cost of saving goes up. But in spite of this wart it was a real pleasure to write *assembly* code for it.
